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ABSTRACT: Hexagonal boron nitride (h-BN) is a promising dielectric material for graphene-based electronic devices. Here we investigate the potential of h-BN gate dielectrics, grown by chemical vapor deposition (CVD), for integration with quasi-freestanding epitaxial graphene (QFEG). We discuss the large scale growth of h-BN on copper foil via a catalytic thermal CVD process and the subsequent transfer of h-BN to a 75 mm QFEG wafer. X-ray photoelectron spectroscopy (XPS) measurements confirm the absence of h-BN/graphitic domains and indicate that the film is chemically stable throughout the transfer process, while Raman spectroscopy indicates a 42% relaxation of compressive stress following removal of the copper substrate and subsequent transfer of h-BN to QFEG. Despite stress-induced wrinkling observed in the films, Hall effect measurements show little degradation (<10%) in carrier mobility for h-BN coated QFEG. Temperature dependent Hall measurements indicate little contribution from remote surface optical phonon scattering and suggest that, compared to HfO(2) based dielectrics, h-BN can be an excellent material for preserving electrical transport properties. Graphene transistors utilizing h-BN gates exhibit peak intrinsic cutoff frequencies >30 GHz (2.4× that of HfO(2)-based devices).
ACS Nano 04/2012; 6(6):5234-41. · 10.77 Impact Factor
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Mark A Fanton,
Joshua A Robinson,
Conor Puls,
Ying Liu,
Matthew J Hollander,
Brian E Weiland, Michael Labella,
Kathleen Trumbull,
Richard Kasarda,
Casey Howsare,
Joseph Stitt,
David W Snyder
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ABSTRACT: We present a novel method for the direct metal-free growth of graphene on sapphire that yields high quality films comparable to that of graphene grown on SiC by sublimation. Graphene is synthesized on sapphire via the simple decomposition of methane at 1425-1600 °C. Film quality was found to be a strong function of growth temperature. The thickness, structure, interface characteristics, and electrical transport properties were characterized in order to understand the utility of this material for electronic devices. Graphene synthesized on sapphire is found to be strain relieved, with no evidence of an interfacial buffer layer. There is a strong correlation between the graphene structural quality and carrier mobility. Room temperature Hall effect mobility values were as high as 3000 cm(2)/(V s), while measurements at 2 K reached values of 10,500 cm(2)/(V s). These films also display evidence of the quantum Hall effect. Field effect transistors fabricated from this material had a typical current density of 200 mA/mm and transconductance of 40 mS/mm indicating that material performance may be comparable to graphene on SiC.
ACS Nano 09/2011; 5(10):8062-9. · 10.77 Impact Factor
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ABSTRACT: We directly demonstrate the importance of buffer elimination at the graphene/SiC(0001) interface for high frequency applications. Upon successful buffer elimination, carrier mobility increases from an average of 800 cm(2)/(V s) to >2000 cm(2)/(V s). Additionally, graphene transistor current saturation increases from 750 to >1300 mA/mm, and transconductance improves from 175 mS/mm to >400 mS. Finally, we report a 10× improvement in the extrinsic current gain response of graphene transistors with optimal extrinsic current-gain cutoff frequencies of 24 GHz.
Nano Letters 08/2011; 11(9):3875-80. · 13.20 Impact Factor
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Matthew J Hollander, Michael Labella,
Zachary R Hughes,
Michael Zhu,
Kathleen A Trumbull,
Randal Cavalero,
David W Snyder,
Xiaojun Wang,
Euichul Hwang,
Suman Datta,
Joshua A Robinson
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ABSTRACT: We explore the effect of high-κ dielectric seed layer and overlayer on carrier transport in epitaxial graphene. We introduce a novel seeding technique for depositing dielectrics by atomic layer deposition that utilizes direct deposition of high-κ seed layers and can lead to an increase in Hall mobility up to 70% from as-grown. Additionally, high-κ seeded dielectrics are shown to produce superior transistor performance relative to low-κ seeded dielectrics and the presence of heterogeneous seed/overlayer structures is found to be detrimental to transistor performance, reducing effective mobility by 30-40%. The direct deposition of high-purity oxide seed represents the first robust method for the deposition of uniform atomic layer deposited dielectrics on epitaxial graphene that improves carrier transport.
Nano Letters 08/2011; 11(9):3601-7. · 13.20 Impact Factor
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ABSTRACT: We investigate graphene transport and structural properties as a function of silicon carbide (SiC) wafer orientation. Terrace step edge density is found to increase with wafer misorientation from SiC(0001). This results in a monotonic increase in average graphene thickness, as well as a 30% increase in carrier density and 40% decrease in mobility up to 0.45° miscut toward (100). Beyond 0.45°, average thickness and carrier density continues to increase; however, carrier mobility is similar to low-miscut angles, suggesting that the interaction between graphene and SiC(0001) may be fundamentally different that of graphene/SiC(10n).
Applied Physics Letters 06/2011; 98(22):222109-222109-3. · 3.84 Impact Factor
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ABSTRACT: We present the integration of epitaxial graphene with thin film dielectric materials for the purpose of graphene transistor development. The impact on epitaxial graphene structural and electronic properties following deposition of Al(2)O(3), HfO(2), TiO(2), and Ta(2)O(5) varies based on the choice of dielectric and deposition parameters. Each dielectric film requires the use of a nucleation layer to ensure uniform, continuous coverage on the graphene surface. Graphene quality degrades most severely following deposition of Ta(2)O(5), while the deposition if TiO(2) appears to improve the graphene carrier mobility. Finally, we discuss the potential of dielectric stack engineering for improved transistor performance.
ACS Nano 04/2010; 4(5):2667-72. · 10.77 Impact Factor
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ABSTRACT: A promising route for the synthesis of large-area graphene, suitable for standard device fabrication techniques, is the sublimation of silicon from silicon carbide at elevated temperatures (>1200 degrees C). Previous reports suggest that graphene nucleates along the (110n) plane, known as terrace step edges, on the silicon carbide surface. However, to date, a fundamental understanding of the nucleation of graphene on silicon carbide is lacking. We provide the first direct evidence that nucleation of epitaxial graphene on silicon carbide occurs along the (110n) plane and show that the nucleated graphene quality improves as the synthesis temperature is increased. Additionally, we find that graphene on the (110n) plane can be significantly thicker than its (0001) counterpart and appears not to have a thickness limit. Finally, we find that graphene along the (110n) plane can contain a high density of structural defects, often the result of the underlying substrate, which will undoubtedly degrade the electronic properties of the material. Addressing the presence of non-uniform graphene that may contain structural defects at terrace step edges will be key to the development of a large-scale graphene technology derived from silicon carbide.
ACS Nano 12/2009; 4(1):153-8. · 10.77 Impact Factor
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ABSTRACT: This paper has been withdrawn due to the adherance to the double submission policies of a refereed journal. Our apologies. Comment: Includes supplimental material
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