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    ABSTRACT: This paper describes a phase-locked loop (PLL) clock generator with low sensitivity to power supply noise. A voltage controlled oscillator employing a source follower reduces power supply noise sensitivity with the proposed power-efficient low-ripple DC-DC converter. Simulated clock jitter is less than ±20 ps, with a 200 mV peak-to-peak sinusoidal noise signal of 1 MHz to 400 MHz applied to a power supply. The proposed PLL simulated in a 0.65 μm double-poly double-metal CMOS process consumes 27 mW at 200 MHz from a 3 V supply. The prototype is under fabrication
    VLSI and CAD, 1999. ICVC '99. 6th International Conference on; 02/1999