Michael J. O'Loughlin

Cree, North Carolina, United States

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Publications (58)12.26 Total impact

  • Wide Bandgap Power Devices and Applications (WiPDA), 2014 IEEE Workshop on, Knoxville, Tenassee; 10/2014
  • IEEE Energy Conversion Congress and Exposition 2014 (ECCE 2014), Pittsburgh, PA, USA; 09/2014
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    ABSTRACT: Since Cree, Inc.'s 2nd generation 4H-SiC MOSFETs were commercially released with a specific on-resistance (RON, SP) of 5 mΩ·cm2 for a 1200 V-rating in early 2013, we have further optimized the device design and fabrication processes as well as greatly expanded the voltage ratings from 900 V up to 15 kV for a much wider range of high-power, high-frequency, and high-voltage energy-conversion and transmission applications. Using these next-generation SiC MOSFETs, we have now achieved new breakthrough performance for voltage ratings from 900 V up to 15 kV with a RON, SP as low as 2.3 mΩ·cm2 for a breakdown voltage (BV) of 1230 V and 900 V-rating, 2.7 mΩ·cm2 for a BV of 1620 V and 1200 V-rating, 3.38 mΩ·cm2 for a BV of 1830 V and 1700 V-rating, 10.6 mΩ·cm2 for a BV of 4160 V and 3300 V-rating, 123 mΩ·cm2 for a BV of 12 kV and 10 kV-rating, and 208 mΩ·cm2 for a BV of 15.5 kV and 15 kV-rating. In addition, due to the lack of current tailing during the bipolar device switching turn-off, the SiC MOSFETs reported in this work exhibit incredibly high frequency switching performance over their silicon counter parts.
    2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD); 06/2014
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    ABSTRACT: This work compares the optical microwave photoconductivity decay (μPCD) and electrical open-circuit voltage decay (OCVD) techniques for measuring the ambipolar carrier lifetime in 4H-silicon carbide (4H-SiC) epitaxial layers. Lifetime measurements were carried out by fabricating P+/intrinsic/N+ (PiN) diodes on 100- μm-thick, 1 × 1014 cm-3 to 4.5 × 1014 cm-3 doped N-type 4 H-SiC epilayers, and measuring the lifetime optically using μPCD prior to metallization, then electrically using OCVD after contact deposition. Both as-grown epilayers as well as epilayers with improved lifetime (via thermal oxidation) were measured using both techniques. The observed ambipolar lifetime was improved from 1.4 μs on an unenhanced wafer to 4 μs on a wafer enhanced through the oxidation process as measured by μPCD. Little difference was observed between the μPCD and OCVD measurements on the unenhanced wafer; the ambipolar lifetime on the enhanced wafer measured by OCVD was approximately 5.5 μs, or 1.5 μs higher than the μPCD measurement. Continuous evaluation of the OCVD transient waveform was necessary due to the high lifetime in the enhanced wafer; shunt resistances included to discharge the P+/N junction capacitance were found to damp the OCVD response and yield low values for the measured lifetime. Simulation of the μPCD measurement including various surface recombination conditions yielded a good match to experimentally observed μPCD measurements for high values of the surface recombination velocity. The OCVD lifetime measurement technique is expected to yield measured lifetime values closer to the physical value due to its independence from surface conditions, provided that the experimental conditions are appropriately chosen.
    Journal of Electronic Materials 03/2014; 43(4). DOI:10.1007/s11664-013-2836-0 · 1.68 Impact Factor
  • Michael John O'Loughlin · Lin Cheng · Albert Augustus Burk JR · Anant Kumar Agarwal
    Ref. No: US Patent App. No. 20140070230 A1, Year: 03/2014
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    ABSTRACT: Advanced high-voltage (≥10 kV) silicon carbide (SiC) devices described in this paper have the potential to significantly impact the system size, weight, high-temperature reliability, and cost of modern variable-speed medium-voltage (MV) systems such as variable speed (VSD) drives for electric motors, integration of renewable energy including energy storage, micro-grids, traction control, and compact pulsed power systems. In this paper, we review the current status of the development of 10 kV-20 kV class power devices in SiC, including MOSFETs, JBS diodes, IGBTs, GTO thyristors, and PiN diodes at Cree. Advantages and weakness of each device are discussed and compared. A strategy for high-voltage SiC power device development is proposed.
    Materials Science Forum 02/2014; 778-780:1089 - 1094. DOI:10.4028/www.scientific.net/MSF.778-780.1089
  • A.A. Burk · D. Tsvetkov · Michael J. O'Loughlin · S. Ustin · L. Garrett · A.R. Powell · J. Seaman · N. Partin
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    ABSTRACT: Latest results are presented for SiC-epitaxial growths employing a novel 6x150-mm/10x100-mm Warm-Wall Planetary Vapor-Phase Epitaxial (VPE) Reactor. The increased throughput offered by this reactor and 150-mm diameter wafers, is intended to reduce the cost per unit area for SiC epitaxial layers, increasing the market penetration of already successful commercial SiC Schottky and MOSFET devices [1]. Increased growth rates of 30-40 micron/hr and short <2 hr fixed-cycle times (including rapid heat-up and cool-down ramps), while maintaining desirable epitaxial layer quality were achieved. Increased quantities of 150-mm epitaxial wafers now allow statistical analysis of their epitaxial layer properties. Specular epitaxial layer morphology was obtained, with morphological defect densities <0.4 cm-2, consistent with projected 5x5 mm die yields averaging 93% for Si-face epitaxial layers between 10 and 30 microns thick. Intrawafer thickness and doping uniformity are good, averaging 1.7% and 5.1% respectively. Wafer-to-wafer doping variation has also been significantly reduced from ~12 [5] to <3% s/mean. Initial results for C-face growths show excellent morphology (97%) but poor doping uniformity (~16%). Wafer shape is relatively unchanged by epitaxial growth consistent with good epitaxial temperature uniformity.
    Materials Science Forum 02/2014; 778-780:113-116. DOI:10.4028/www.scientific.net/MSF.778-780.113
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    ABSTRACT: A 1 cm x 1 cm 4H-SiC N-IGBT exhibited a blocking voltage of 20.7 kV with a leakage current of 140 μA, which represents the highest blocking voltage reported from a semiconductor power switching device to this date. The device used a 160 μm thick drift layer and a 1 μm thick Field-Stop buffer layer, and showed a VF of 6.4 V at an IC of 20 A, and a differential Ron,sp of 28 mΩ-cm2. Switching measurements with a supply voltage of 8 kV were performed, and a turn-off time of 1.1 μs and turn-off losses of 10.9 mJ were measured at 25°C, for a 8.4 mm x 8.4 mm device with 140 μm drift layer and 2 μm F-S buffer layer. The turn-off losses were reduced by approximately 50% by using a 5 μm F-S buffer layer. A 55 kW, 1.7 kV to 7 kV boost converter operating at 5 kHz was demonstrated using the 4H-SiC N-IGBT, and an efficiency value of 97.8% was reported.
    Materials Science Forum 02/2014; 778-780:1030-1033. DOI:10.4028/www.scientific.net/MSF.778-780.1030
  • Robert E. Stahlbush · Nadeemullah A. Mahadik · Michael J. O'Loughlin
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    ABSTRACT: Suppression of basal plane dislocations (BPDs) from critical epitaxial drift layer has occurred mainly by converting BPDs in the substrate into threading edge dislocations before the BPDs enter the drift layer. As optimized epitaxial growth has produced drift layers free of BPDs originating from the substrate over a large fraction of the wafer, other sources of BPDs have become important. One source of BPDs introduced during epitaxial growth is from inclusions, which mainly consist of misoriented 4H-SiC. Inclusions are surrounded by a local cluster of BPDs and in thick, low-BPD epitaxy the outermost BPDs glide centimeters from the inclusion forming a much larger damaged area. The details of BPD migration from inclusions are discussed.
    Materials Science Forum 02/2014; 778-780:309-312. DOI:10.4028/www.scientific.net/MSF.778-780.309
  • 55th Electronic Material Conference (EMC13), South Bend, IN, USA; 06/2013
  • Plasma Science (ICOPS), 2013 Abstracts IEEE International Conference on, San Francisco, CA, USA; 06/2013
  • Lin Cheng · Anant K. Agarwal · Michael J. O'Loughlin · Albert A. Burk · John W. Palmour
    Ref. No: US Patent App. No. 20130026493 A1, Year: 01/2013
  • Materials Science Forum 01/2013; 740-742.
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    ABSTRACT: The latest developments in ultra high voltage 4H-SiC IGBTs are presented. A 4H-SiC P-IGBT, with a chip size of 8.4 mm x 8.4 mm and an active area of 0.32 cm(2), which is double the active area of the previously reported devices [1], exhibited a blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 41 m Omega.cm(2) with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 17 kV, and demonstrated a room temperature differential specific on-resistance of 25.6 m Omega.cm(2) with a gate bias of 20 V. Field-Stop buffer layer design was used to control the charge injection from the backside. A comparison between N- and P- IGBTs, and the effects of different buffer designs, are presented.
    Materials Science Forum 01/2013; 740-742:954-957. DOI:10.4028/www.scientific.net/MSF.740-742.954
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    ABSTRACT: The need for high voltage solid-state power electronic devices for advanced power distribution and energy conversion has grown rapidly in recent years, especially for pulsed power applications that require high turn-on di/dt. However, current power converters built with silicon (Si) switches are quite bulky and inefficient, making their utilization difficult in practical energy conversion and power distribution systems. The development of high-voltage power devices based on wide bandgap semiconductor such as silicon carbide (SiC) has attracted great attention due to its superior material properties over silicon. Among the high-voltage SiC power devices, SiC gate turn-off thyristor (GTO) offers excellent current handling, very high voltage blocking, and fast turn-off capabilities. SiC GTO also exhibits lower forward voltage drop than the IGBT-based switch at high injection-level currents, resulting in lower power losses during normal operation. In this paper, we report our recently developed 2 cm2, 20 kV SiC p-type gate turnoff GTO thyristor with very low differential on-resistance for advanced pulsed power applications.
    Pulsed Power Conference (PPC), 2013 19th IEEE; 01/2013
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    ABSTRACT: A 1 cm × 1 cm 4H-SiC N-IGBT exhibited a blocking voltage of 20.7 kV with a leakage current of 140 μA, which represents the highest blocking voltage reported from an MOS semiconductor power switching device to date. The device showed a VF of 6.4 V at an IC of 20 A, and a differential Ron,sp of 28 mΩ-cm2. Temperature insensitive on-state characteristics were demonstrated. Switching measurements with a supply voltage of 8 kV were performed, and a turn-off time of 720 ns and a turn-off loss of 5.4 mJ were measured at 25°C, for a 8.4 mm × 8.4 mm device with 140 μm drift layer and 5 μm Field Stop buffer layer. It was demonstrated that the charge injection from the backside can be controlled by varying the thickness of the Field-Stop buffer layer. A 55 kW, 1.7 kV to 7 kV boost converter operating at 5 kHz was demonstrated using the 4H-SiC N-IGBT, and an efficiency value of 97.8% was reported.
    Wide Bandgap Power Devices and Applications (WiPDA), 2013 IEEE Workshop on; 01/2013
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    ABSTRACT: In this paper, we report our recently developed 1 cm(2), 15 kV SiC p-GTO with an extremely low differential on-resistance (R-ON,R-diff) of 4.08 m Omega.cm(2) at a high injection-current density (J(AK)) of 600 similar to 710 A/cm(2). The 15 kV SiC p-GTO was built on a 120 mu m, 2x10(14)/cm(3) doped p-type SiC drift layer with a device active area of 0.521 cm(2). Forward conduction of the 15 kV SiC p-GTO was characterized at 20 degrees C and 200 degrees C. Over this temperature range, the R-ON,R-diff at J(AK) of 600 similar to 710 A/cm(2) decreased from 4.08 m Omega.cm(2) at 20 degrees C to 3.45 m Omega.cm(2) at J(AK) of 600 similar to 680 A/cm(2) at 200 degrees C. The gate to cathode blocking voltage (V-GK) was measured using a customized high-voltage test setup. The leakage current at a V-GK of 15 kV were measured 0.25 mu A and 0.41 mu A at 20 degrees C and 200 degrees C respectively.
    Materials Science Forum 01/2013; 740-742:978-981. DOI:10.4028/www.scientific.net/MSF.740-742.978
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    ABSTRACT: In this work, we report our recently developed 16 kV, 1 cm(2), 4H-SiC PiN diode results. The SiC PiN diode was built on a 120 mu m, 2x10(14)/cm(3) doped n-type SiC drift layer with a device active area of 0.5175 cm(2). Forward conduction of the PiN diode was characterized at temperatures from 20 degrees C to 200 degrees C. At high injection-current density (J(F)) of 350 similar to 400 A/cm(2), the differential on-resistance (R-ON,R-diff) of the SiC PiN diode decreased from 6.08 m Omega.cm(2) at 20 degrees C to 5.12 m Omega.cm(2) at 200 degrees C, resulting in a very small average temperature coefficient of -5.33 mu Omega.cm(2)/degrees C, while the forward voltage drop (V-F) at 100 A/cm(2) reduced from 4.77 V at 20 degrees C to 4.17 V at 200 degrees C. This is due to an increasing high-level carrier lifetime with an increase in temperature, resulting in reduced forward voltage drop. We also observed lower R-ON,R-diff at higher injection-current densities, suggesting that a higher carrier lifetime is needed in this lightly doped n-type SiC thick epi-layer in order to achieve full conductivity modulation. The anode to cathode reverse blocking leakage current was measured as 0.9 mu A at 16 kV at room temperature.
    Materials Science Forum 01/2013; 740-742:895-898. DOI:10.4028/www.scientific.net/MSF.740-742.895
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    ABSTRACT: The effect of extended defects on carrier lifetime was investigated in 140 um thick 4H-SiC epilayers using whole wafer ultraviolet photoluminescence (UVPL) and microwave photoconductive decay (uPCD) mapping. Half-loop arrays (HLA) seen in the UVPL images showed a corresponding lifetime degradation in the same region, even before expansion of the HLAs to form SFs. Lifetime lowering was also seen for a defect comprising of a small 3C-SiC inclusion with a larger misoriented 4H-SiC region. Additionally, formation of slip planes after high temperature annealing was observed, which consequently shows a lifetime reduction in that region.
    Materials Science Forum 05/2012; 717-720:297-300. DOI:10.4028/www.scientific.net/MSF.717-720.297
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    ABSTRACT: Initial results are presented for SiC-epitaxial growths employing a novel 6x150-mm/10x100-mm Warm-Wall Planetary Vapor-Phase Epitaxial (VPE) Reactor. The increased areal throughput offered by this reactor and 150-mm diameter wafers, is intended to reduce the cost per unit area for SiC epitaxial layers, increasing the market penetration of already successful commercial SiC Schottky and MOSFET devices [1]. Growth rates of 20 micron/hr and short <2 hr fixed-cycle times (including rapid heat-up and cool-down ramps), while maintaining desirable epitaxial layer quality were achieved. No significant change in 150 mm diameter wafer shape is observed upon epitaxial growth consistent with good-quality, low-stress substrates and low (<5 degrees C) cross-wafer epitaxial reactor temperature variation. Specular epitaxial layer morphology was obtained, with morphological defect densities consistent with projected 5x5 mm die yields as high as 80% and surface roughness, Ra, of 0.3 nm. Intrawafer thickness uniformity is good, averaging only 1.6% and within a run wafer-to-wafer thickness variation is 2.7%. N-type background doping densities less that 1E14 cm(-3) have been measured by CV. Doping uniformity and wafer-to-wafer variation currently average similar to 12% requiring further improvement. The first 100 mu m thick 150-mm diameter epitaxial growths are reported.
    Materials Science Forum 05/2012; 717-720:75-80. DOI:10.4028/www.scientific.net/MSF.717-720.75