Ki Hoon Kim

Publications (2)0 Total impact

• Conference Proceeding: A real-time finite line detection system based on FPGA

  Dongkyun Kim, Seung Hun Jin, Nguyen Tuong Thuy, Ki Hoon Kim, Jae Wook Jeon
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  ABSTRACT: Image processing and analysis are active research topics. An intelligent vehicle and a service robot require these techniques. In particular, there is a big demand for line detection because it has a wide range of applications. The line features in an image are used for object identification, robot navigation, and intelligent vehicle control. To detect the lines, a Hough transform is generally used. The Hough transform has good detection results and it is robust to noise, but it takes a long time to execute and it requires a great deal of memory to store the parameter space. This paper proposes a dedicated line detection hardware system. To increase the processing speed, it has a parallel Hough transform unit, and it partitions the parameter space to decrease the memory requirements. It can detect not only the line parameters, but also the exact start and end points of each line, and it sorts these lines by length. It can display the detected line on a monitor via the DVI interface. This system is designed with VHDL and implemented on an XC4VLX200 FPGA. The device usage is about 15% and the maximum clock frequency is 67 MHz. It can detect up to 256 lines in one image frame and it can process up to 149 frames per second. The simulation and real experimental results are given to verify the system performance.
  Industrial Informatics, 2008. INDIN 2008. 6th IEEE International Conference on; 08/2008
• Conference Proceeding: Real-time skeletonization using FPGA

  Ki Hoon Kim, Pham Dai Xuan, Pham Cong Thien, Jae Wook Jeon
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  ABSTRACT: Thinning algorithms(or skeletonization) that extract feature parameters from an image are widely used in image processing. One of the most important issues in thinning is to reduce the execution time. Thus, many thinning algorithms have been proposed. But few attempts have been made to implement the thinning algorithms in real-time. The implementation of real-time skeletonization that has a large number of calculations is very difficult. This paper proposes hardware architecture that can output the thinned image to synchronize with the input image. The proposed architecture is implemented using the FPGA(field programable gate array) based vision system.
  Control, Automation and Systems, 2007. ICCAS '07. International Conference on; 11/2007