J. Michel

University of Strasbourg, Strasburg, Alsace, France

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Publications (8)2.95 Total impact

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    ABSTRACT: In this paper, we aim at developing an analog spiking neural network (SNN) for reinforcing the performance of conventional cardiac resynchronization therapy (CRT) devices (also called biventricular pacemakers). Targeting an alternative analog solution in 0.13-μm CMOS technology, this paper proposes an approach to improve cardiac delay predictions in every cardiac period in order to assist the CRT device to provide real-time optimal heartbeats. The primary analog SNN architecture is proposed and its implementation is studied to fulfill the requirement of very low energy consumption. By using the Hebbian learning and reinforcement learning algorithms, the intended adaptive CRT device works with different functional modes. The simulations of both learning algorithms have been carried out, and they were shown to demonstrate the global functionalities. To improve the realism of the system, we introduce various heart behavior models (with constant/variable heart rates) that allow pathologic simulations with/without noise on the signals of the input sensors. The simulations of the global system (pacemaker models coupled with heart models) have been investigated and used to validate the analog spiking neural network implementation.
    IEEE Transactions on Neural Networks 07/2011; · 2.95 Impact Factor
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    ABSTRACT: The target of this research is to develop an analog spiking neural network in order to improve the performance of biventricular pacemakers, which is also known as Cardiac Resynchronization Therapy (CRT) devices. By using the reinforcement learning algorithm, this paper proposes an approach improving cardiac delay predictions in every cardiac period so as to assist the CRT device to provide real-time optimal heartbeats. The simulation of the reinforcement learning algorithm has also been carried out and illustrated.
    International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France; 01/2010
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    ABSTRACT: In order to solve two major bottlenecks of the analog design flow: the time-to-market and the production yield, we introduce in this paper a design tool for measuring the robustness capability of the analog circuit topologies with the guarantee of fulfilling all the design specifications. With this measure, we can describe the feasible subspace by using the set inversion algorithm. A robustness estimation example of a differential pair of a miller CMOS OTA is shown to illustrate this method.
    Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), 2010 XIth International Workshop on; 01/2010
  • Yannick Herve, Jacques Michel
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    ABSTRACT: To design a system the designer has to establish equations of performances over available adjustments. These equations are non linear, implicit or explicit, static or dynamic with no reversal form. The game is to find an efficient method to determine the good value of adjustments in order to respect restrictions on performances (or specifications). These methods are domain specific and often tiresome and unwieldy. We show in this paper there exists an other point of view on this general problem with the help of a branch of mathematics: The arithmetic of intervals.
    Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on; 07/2008
  • J. Michel, F. Schwartz
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    ABSTRACT: We present in this paper a new method for sizing analogue circuits using interval analysis. This approach enables to enclose the space of solutions with certainty and to compute a guaranteed space useful for the final optimizers. Experimental implementations of this methodology are proposed through two sizing examples: a linear and a non-linear circuit.
    Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on; 07/2008
  • Qing Sun, F. Schwartz, J. Michel, R. Rom
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    ABSTRACT: The goals of this research are to develop an analog spiking neural network so as to improve the performance of biventricular pacemaker (CRT devices). Implantation in silicon uses the analogical neural network approach that requires the development of a technical solution satisfying the requirement of very low energy consumption. Targeting an alternative analog solution in 0.18 mum CMOS technology, this paper presents a new approach in analog spiking neural network for the delay prediction by using a Hebbian learning algorithm.
    Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on; 07/2008
  • J. Michel, Y. Herve
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    ABSTRACT: An analog neural network VHDL-AMS model is developed to analyze the performances of an IC architecture associated with a learning algorithm. We compare here an electrical simulation of a current mode architecture dedicated to deep submicronics technologies with a formal MATLAB<sup>™</sup> model. This comparison allows researching suitability between architecture and algorithm to optimize the learning speed versus the classification precision. It allows also to study the robustness of architecture versus electrical noise, component dispersions or memory loss and the robustness of an algorithm versus noise in the data's.
    Industrial Electronics, 2004 IEEE International Symposium on; 06/2004
  • XIIIèmes Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM'2010).