D. Nair

Publications (4)0 Total impact

• Conference Proceeding: Scaling of 32nm low power SRAM with high-K metal gate

  H.S. Yang, R. Wong, R. Hasumi, Y. Gao, N.S. Kim, D.H. Lee, S. Badrudduza, D. Nair, M. Ostermayr, H. Kang, [......], S. Samavedam, D. Jaeger, C.V. Baiocco, M. Sherony, M. Khare, C. Lage, J. Pape, J. Sudijono, A.L. Steegen, S. Stiffler
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  ABSTRACT: This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum² and 0.124 mum². SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG T_inv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 mum² cell to meet low power application requirements.
  Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
• Conference Proceeding: A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

  X. Chen, S. Samavedam, V. Narayanan, K. Stein, C. Hobbs, C. Baiocco, W. Li, D. Jaeger, M. Zaleski, H.S. Yang, [......], S. Pandey, D. Tekleab, A. Thean, M. Sherony, C. Lage, J. Sudijono, R. Lindsay, J.H. Ku, M. Khare, A. Steegen
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  ABSTRACT: For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum². Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V V_dd with a low cost process. With this high performance transistor, V_dd can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at L_gate = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.
  VLSI Technology, 2008 Symposium on; 07/2008
• Source

  Available from: utexas.edu

  Article: Bayesian recognition of targets by parts in second generation forward looking infrared images

  D Nair, J K Aggarwal
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  ABSTRACT: This paper presents a system for the recognition of targets in second generation forward looking infrared images (FLIR). The recognition of targets is based on a methodology for recognition of two-dimensional objects using object parts. The methodology is based on a hierarchical, modular structure for object recognition. In the most general form, the lowest level consists of classifiers that are trained to recognize the class of the input object, while at the next level, classifiers are trained to recognize specific objects. At each level, the objects are recognized by their parts, and thus each classifier is made up of modules, each of which is an expert on a specific part of the object. Each modular expert is trained to recognize one part under different viewing angles and transformations. A Bayesian realization of the proposed methodology is presented in this paper, in which the expert modules represent the probability density functions of each part, modeled as a mixture of densities to incorporate different views (aspects) of each part. Recognition relies on the sequential presentation of the parts to the system, without using any relational information between the parts. A new method to decompose a target into its parts and results obtained for target recognition in second generation FLIR images are also presented here. 2000 Elsevier Science B.V. All rights reserved.
  Image Vision Comput. 01/2000; 18.
• Source

  Available from: cvrc.ece.utexas.edu

  Article: Bayesian recognition of targets by parts in second generation forward looking infrared images

  D. Nair, J.K. Aggarwal
  [show abstract] [hide abstract]
  ABSTRACT: This paper presents a system for the recognition of targets in second generation forward looking infrared images (FLIR). The recognition of targets is based on a methodology for recognition of two-dimensional objects using object parts. The methodology is based on a hierarchical, modular structure for object recognition. In the most general form, the lowest level consists of classifiers that are trained to recognize the class of the input object, while at the next level, classifiers are trained to recognize specific objects. At each level, the objects are recognized by their parts, and thus each classifier is made up of modules, each of which is an expert on a specific part of the object. Each modular expert is trained to recognize one part under different viewing angles and transformations. A Bayesian realization of the proposed methodology is presented in this paper, in which the expert modules represent the probability density functions of each part, modeled as a mixture of densities to incorporate different views (aspects) of each part. Recognition relies on the sequential presentation of the parts to the system, without using any relational information between the parts. A new method to decompose a target into its parts and results obtained for target recognition in second generation FLIR images are also presented here.
  Image and Vision Computing.