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ABSTRACT: Mainstream electronic designs are realized by Systems-on-Chips (SoCs) that push the limits of integration. The advancement of manufacturing technologies in terms of integration leads us to SoCs with many (e.g., 10-1000) digital units (e.g., processor cores, controllers, storage, application-specific units) that need to be interconnected in an efficient and reliable way. The Network-on-Chip (NoC) design paradigm emerged recently as a promising alternative to classical bus-based communication architectures. Aside from better predictability and lower power consumption, the NoC approach offers greater scalability compared to previous solutions for on-chip communication. The design flow of NoCs include several key issues. Among other parameters, the decision of where cores have to be topologically mapped and also the routing algorithm represent two highly correlated design problems that must be carefully solved for any given application in order to optimize different performance metrics. The strong correlation between the different parameters often makes that the optimization of a given performance metric has a negative effect on a different performance metric. In this paper we propose a new strategy that simultaneously refines the mapping and the routing function to determine the Pareto optimal configurations which optimize average communication delay and routing robustness. The proposed strategy has been applied on both synthetic and real traffic scenarios. The obtained results show how the solutions found by the proposed approach outperforms those provided by other approaches proposed in literature, in terms of both performance and fault tolerance.
Journal of Universal Computer Science. 01/2012; 18(7):937-969.
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ABSTRACT: Multi-objective evolutionary algorithms (MOEAs) have received increasing interest in industry because they have proved to be powerful optimizers. Despite the great success achieved, however, MOEAs have also encountered many challenges in real-world applications. One of the main difficulties in applying MOEAs is the large number of fitness evaluations (objective calculations) that are often needed before an acceptable solution can be found. There are, in fact, several industrial situations in which fitness evaluations are computationally expensive and the time available is very short. In these applications efficient strategies to approximate the fitness function have to be adopted, looking for a trade-off between optimization performance and efficiency. This is the case in designing a complex embedded system, where it is necessary to define an optimal architecture in relation to certain performance indexes while respecting strict time-to-market constraints. This activity, known as design space exploration (DSE), is still a great challenge for the EDA (electronic design automation) community. One of the most important bottlenecks in the overall design flow of an embedded system is due to simulation. Simulation occurs at every phase of the design flow and is used to evaluate a system which is a candidate for implementation. In this paper we focus on system level design, proposing an extensive comparison of the state-of-the-art of MOEA approaches with an approach based on fuzzy approximation to speed up the evaluation of a candidate system configuration. The comparison is performed in a real case study: optimization of the performance and power dissipation of embedded architectures based on a Very Long Instruction Word (VLIW) microprocessor in a mobile multimedia application domain. The results of the comparison demonstrate that the fuzzy approach outperforms in terms of both performance and efficiency the state of the art in MOEA strategies applied to DSE of a parameterized embedded system.
Applied Soft Computing 04/2011; · 2.61 Impact Factor
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IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2011; 30:774-786.
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IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2010; 29:426-440.
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13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France; 01/2010
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IET Computers & Digital Techniques. 01/2009; 3:413-429.
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12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece; 01/2009
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IEEE Trans. Parallel Distrib. Syst. 01/2009; 20:316-330.
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ABSTRACT: As the number of cores in a chip increases, the role played by the communication system becomes more and more central. An on-chip communication infrastructure based on the Network-on-Chip (NoC) paradigm is today recognized as the most effective and scalable solution able to deal with the communication issues that will characterize the next generation of many-cores architectures. An ever more significant fraction of the overall chip area is devoted to support advanced and reliable communication protocols making the energy resources used for communication starting to compete with the ones spent for computation. Amongst the communication resources, as technology shrinks, the power ratio between NoC links and routers increases making the links becoming more power-hungry than routers. In this paper we propose a novel endto-end data encoding scheme which exploits the wormhole technique commonly used in NoC-based system to reduce power dissipated by the NoC links. We assess the proposed encoding scheme on a set of representative data streams showing that it is possible to reduce the power contribution of both the self switching activity and the coupling switching activity in inter-routers links. As results, we obtain a reduction in total power dissipation and energy consumption up to 26% and 9% respectively without any significant degradation in terms of both performance and silicon area. The encoder and decoder logic is integrated in the network interface and is transparent to the underling NoC.
12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece; 01/2009
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ABSTRACT: Efficient and deadlock-free routing is critical to the performance of networks-on-chip. The effectiveness of any adaptive routing algorithm strongly depends on the underlying selection strategy. A selection function is used to select the output channel where the packet will be forwarded on. In this paper we present a novel selection strategy that can be coupled with any adaptive routing algorithm. The proposed selection strategy is based on the concept of Neighbors-on-Path the aims of which is to exploit the situations of indecision occurring when the routing function returns several admissible output channels. The overall objective is to choose the channel that will allow the packet to be routed to its destination along a path that is as free as possible of congested nodes. Performance evaluation is carried out by using a flit-accurate simulator under traffic scenarios generated by both synthetic and real applications. Results obtained show how the proposed selection strategy applied to the Odd-Even routing algorithm yields an improvement in both average delay and saturation point up to 20% and 30% on average respectively, with a minimal overhead in terms of area occupation. In addition, a positive effect on total energy consumption is also observed under near-congestion packet injection rates.
IEEE Transactions on Computers 07/2008; 57(6):809-820. · 1.10 Impact Factor
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TACO. 01/2008; 5.
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11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008; 01/2008
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ABSTRACT: In this paper we assess the use of high performance computing in design space exploration of a complex highly parameterized very long instruction word based system-on-a-chip platform. Experiments show that the conventional belief of linear decrease in exploration time as the number of available processors increases is discredited starting from a relatively low number of processors mainly due to communication overhead and I/O bottleneck.
11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008; 01/2008
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ABSTRACT: The procedure of evaluating the results of a clustering algorithm is know under the term cluster validity. In general terms,
cluster validity criteria can be classified in three categories: internal, external and relative. In this work we focus on
the external criteria, which evaluate the results of a clustering algorithm based on a pre-specified structure S, that pertains to the data but which is independent of it. Usually S is a crisp partition (i.e. the data labels), and the most common approach for external validation of fuzzy partitions is
to apply measures defined for crisp partitions to fuzzy partitions, using crisp partitions derived (hardened) from them. In
this paper we discuss fuzzy generalizations of two well known crisp external measures, which are able to assess the quality
of a partition U without the hardening of U. We also define a new external validity measure, that we call DNC index, useful for comparing a fuzzy U to a crisp S. Numerical examples based on four real world data sets are given, demonstrating the higher reliability of the DNC index.
07/2007: pages 491-501;
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FUZZ-IEEE 2007, IEEE International Conference on Fuzzy Systems, Imperial College, London, UK, 23-26 July, 2007, Proceedings; 01/2007
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Journal of Circuits, Systems, and Computers. 01/2007; 16:819-846.
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21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA; 01/2007
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ABSTRACT: A reduction in the time-to-market has led to widespread use of pre-designed parametric architectural solutions known as system-on-a-chip (SoC) platforms. A system designer has to configure the platform in such a way as to optimize it for the execution of a specific application. Very frequently, however, the space of possible configurations that can be mapped onto a SoC platform is huge and the computational effort needed to evaluate a single system configuration can be very costly. In this paper we propose an approach which tackles the problem of design space exploration (DSE) in both of the fronts of the reduction of the number of system configurations to be simulated and the reduction of the time required to evaluate (i.e., simulate) a system configuration. More precisely, we propose the use of Multi-objective Evolutionary Algorithms as optimization technique and Fuzzy Systems for the estimation of the performance indexes to be optimized. The proposed approach is applied on a highly parameterized SoC platform based on a parameterized VLIW processor and a parameterized memory hierarchy for the optimization of performance and power dissipation. The approach is evaluated in terms of both accuracy and efficiency and compared with several established DSE approaches. The results obtained for a set of multimedia applications show an improvement in both accuracy and exploration time.
Journal of Systems Architecture 01/2007; · 0.44 Impact Factor
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Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006; 01/2006
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IEEE T. Fuzzy Systems. 01/2006; 14:528-541.
