John A. Chandy

University of Connecticut, Storrs, Connecticut, United States

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Publications (61)17.21 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: Computation within a network switch accelerates data processing.•FPGA implementations of modules to process data on the fly through the network.•Data processing modules include data search, sort, k-min/k-max, and k-means clustering.
    Future Generation Computer Systems 11/2014; · 2.64 Impact Factor
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    ABSTRACT: In this paper, we are presenting fast digital to analog convertor designs using Spatial Waveform Switched FETs (SWSFET). SWSFET was introduced by Jain et.al. These FETs have multiple channels stacked vertically. The Carrier wavefunction switches from one channel to another with the application of different gate voltages. Designs of multi-bit SRAM, logic and sequential cells using SWSFETs have been demonstrated. Here we are introducing the use of SWSFET in mixed signal architectures. Single cycle architectures for two-bit, four-bit and eight-bit analog to digital converters are presented. Four bit architecture has been simulated and results are discussed. SWSFET presents the opportunity with its multiple stacked channel features to extend the Moors law using next generation of devices.
    International Journal of High Speed Electronics and Systems 05/2014; 23(01n02).
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    ABSTRACT: In this paper, we propose a new architecture for analog-to-digital converters (ADCs) using multistate spatial wavefunction-switched field-effect transistors (SWSFETs). SWSFETs are multiple quantum coupled well devices, where the wells are stacked vertically and the electron wavefunction switches from one well to another with the change in gate voltage. Quantum mechanical simulations of 3-well InGaAs-AlInAs SWSFET structures are presented. The designs and simulations of 2-bit and 3-bit ADCs using SWSFETs result in low power consumption and reduced device count which improves the speed of the data conversion.
    International Journal of High Speed Electronics and Systems 05/2014; 23(01n02).
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    ABSTRACT: Spatial wave-function switched field effect transistor (SWSFET) switches the current flow between different channels inside the FET based on the applied voltage in its gate terminal. SWSFET can be used to implement multi-valued logic circuit with less number of circuit elements. Recently we presented unipolar inverter circuit using SWSFET. In this paper we develop a circuit model of SWSFET based on BSIM 3.2.0 and BSIM 3.2.4 and implement membership function using that circuit model of SWSFET. The spatial wave-function switched field effect transistor (SWSFET) has two or three low band-gap quantum well channels inside the substrate of the semiconductor. Applied voltage at the gate region of the SWSFET, switches the charge carrier concentration in different channels from source to drain region. A circuit model of SWSFET is developed in BSIM 3.2.0. Membership function is implemented using the circuit model of the SWSFET. Membership function implementation using less number of SWSFET will reduce the device count in future analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuits.
    International Journal of High Speed Electronics and Systems 05/2014; 23(01n02).
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    ABSTRACT: This paper describes novel multibit static random-access memories (SRAMs) implemented using four-channel spatial wavefunction switched field-effect transistors (SWS FETs) with Ge quantum wells and ZnSSe barriers. A two-bit SRAM cell consists of two back-to-back connected four-channel SWS FETs, where each SWS FET serves as a quaternary inverter. This architecture results in a reduction of the field-effect transistor (FET) count by 75% and data interconnect density by 50%. The designed two-bit SRAM cell is simulated using Berkeley short-channel insulated-gate field-effect transistor equivalent-channel models (for 25-nm FETs). In addition, the binary interface logic and conversion circuitry are designed to integrate the SWS SRAM technology. Our motivation is to stack up multiple bits on a single SRAM cell without multiplying the transistor count. The concept of spatial wavefunction switching (SWS) in the FET structure has been verified experimentally for two- and four-well structures. Quantum simulations exhibiting SWS in four-well Ge SWS FET structures, using the ZnSe/ZnS/ZnMgS/ZnSe gate insulator, are presented. These structures offer higher contrast than Si-SiGe SWS FETs.
    Journal of Electronic Materials 11/2013; 42(11). · 1.64 Impact Factor
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    ABSTRACT: Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiOx -cladded Si or GeOx -cladded Ge quantum dots (QDs) with asymmetric dot sizes. An alternative method is to use both SiOx -cladded Si and GeOx -cladded Ge QDs in QDGFETs. In this paper, we present experimental verification of four-state behavior observed in a QDGFET with cladded Si and Ge dots site-specifically self-assembled in the gate region over a thin SiO2 tunnel layer on a Si substrate. This paper also investigates the use of lattice-matched high-κ ZnS-ZnMgS-ZnS layers as a gate insulator in mixed-dot Si QDGFETs. Quantum-mechanical simulation of the transfer characteristic (I D–V G) shows four-state behavior with two intermediate states between the conventional ON and OFF states.
    Journal of Electronic Materials 11/2013; 42(11). · 1.64 Impact Factor
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    ABSTRACT: Three-state behavior has been demonstrated in Si and InGaAs field-effect transistors (FETs) when two layers of cladded quantum dots (QDs), such as SiOx -cladded Si or GeOx -cladded Ge, are assembled on the thin tunnel gate insulator. This paper describes FET structures that have the potential to exhibit four states. These structures include: (1) quantum dot gate (QDG) FETs with dissimilar dot layers, (2) quantum dot channel (QDC) with and without QDG layers, (3) spatial wavefunction switched (SWS) FETs with multiple coupled quantum well channels, and (4) hybrid SWS–QDC structures having multiple drains/sources. Four-state FETs enable compact low-power novel multivalued logic and two-bit memory architectures. Furthermore, we show that the performance of these FETs can be enhanced by the incorporation of II–VI nearly lattice-matched layers in place of gate oxides and quantum well/dot barriers or claddings. Lattice-matched high-energy gap layers cause reduction in interface state density and control of threshold voltage variability, while providing a higher dielectric constant than SiO2. Simulations involving self-consistent solutions of the Poisson and Schrödinger equations, and transfer probability rate from channel (well or dot layer) to gate (QD layer) are used to design sub-12-nm FETs, which will aid the design of multibit logic and memory cells.
    Journal of Electronic Materials 11/2013; 42(11). · 1.64 Impact Factor
  • S. Karmakar, J.A. Chandy, F.C. Jain
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    ABSTRACT: In this paper, we discuss logic circuit designs using the circuit model of three-state quantum dot gate field effect transistors (QDGFETs). QDGFETs produce one intermediate state between the two normal stable ON and OFF states due to a change in the threshold voltage over this range. We have developed a simplified circuit model that accounts for this intermediate state. Interesting logic can be implemented using QDGFETs. In this paper, we discuss the designs of various two-input three-state QDGFET gates, including NAND- and NOR-like operations and their application in different combinational circuits like decoder, multiplier, adder, and so on. Increased number of states in three-state QDGFETs will increase the number of bit-handling capability of this device and will help us to handle more number of bits at a time with less circuit elements.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2013; 21(5):793-806. · 1.22 Impact Factor
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    ABSTRACT: Spatial Wavefunction-Switched (SWS) Field-Effect Transistors (FETs) consist of inversion layers comprising two or more coupled quantum wells (QWs). Carriers can be localized in any of the wells and vertically transferred between them by changing the gate voltage. In addition, carriers can also be laterally transferred between adjacent SWSFET devices by the manipulation of the gate voltages (Vg). This enables processing of two more bits simultaneously by changing the spatial location of the carrier ensemble wavefunction, which in turn determines the state of the device [e.g., electrons in well W2 (01), in W1 (10), in both (11), in neither (00)]. Experimentally, the capacitance-voltage data, having a distinct peak, has been presented in InGaAs-AlInAs two-quantum well structures. The peak(s) are attributed to the appearance of carriers, first in the lower well and subsequently their transfer to the upper well. Use of multiple channels allows for CMOS-like configuration with both transistors having n-channel mobilities. Simulation of an InGaAs SWS inverter computes a gate delay of 0.24ps. A cut-off frequency in excess of 8THz is computed for 12nm channel length InGaAs SWSFETs. Examples, including logic gates and a 3-bit full-adder, are presented to show the reduction of device count when SWS-FETs are employed.
    International Journal of High Speed Electronics and Systems 04/2012; 20(03).
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    ABSTRACT: Three-state behavior has been demonstrated in Si and InGaAs quantum dot gate (QDG) field-effect transistorsootnotetextS. Karmakar, et al., J. Electronic Materials, 40, 1746, 2011.^,ootnotetextF Jain, J. Electronic Materials, 40, 1717, 2011. (FETs). Recently, spatial wavefunction switchedootnotetextIbid. (SWS) and quantum dot channelootnotetextF. Jain et al., Proc. II-VI Workshop, Oct.2011. (QDC) FETs have been reported to exhibit four-state operation. This paper presents simulations of versatile combinations of SWS features in QDC channels to optimally design multi-state transport in FETs that have the potential of scaling to sub-12nm regime. A QDC-FET channel is modeled as having superlattice-like mini-energy bands where the carrier wavefunctions are transferred across the channel as drain voltage is changed, producing step-like multi-state electrical characteristics. This behavior is analogous to that of single electron transistors.ootnotetextS. J. Shin, et al., Appl. Phys. Lett. 97, 103101, 2010. The difference is that QDC devices use more than a few electrons and operate at room temperature. The SWS feature additionally provides carrier transfer from lower to upper dot layer(s) in a QDC having more than one layer of quantum dots.
    02/2012;
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    ABSTRACT: High-performance computing (HPC) storage systems rely on access coordination to ensure that concurrent updates do not produce incoherent results. HPC storage systems typically employ pessimistic distributed locking to provide this functionality in cases where applications cannot perform their own coordination. This approach, however, introduces significant performance overhead and complicates fault handling. In this work we evaluate the viability of optimistic conditional storage operations as an alternative to distributed locking in HPC storage systems. We investigate design strategies and compare the two approaches in a prototype object storage system using a parallel read/modify/write benchmark. Our prototype illustrates that conditional operations can be easily integrated into distributed object storage systems and can outperform standard coordination primitives for simple update workloads. Our experiments show that conditional updates can achieve over two orders of magnitude higher performance than pessimistic locking for some parallel read/modify/write workloads.
    High Performance Computing, Networking, Storage and Analysis (SCC), 2012 SC Companion:; 01/2012
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    ABSTRACT: In this paper, we present the design and implementation of an active storage framework for object storage devices. The framework is based on the use of virtual machines/execution engines to execute function code downloaded from client applications. We investigate the issues involved in supporting multiple execution engines. Allowing user-downloadable code fragments introduces potential safety and security considerations, and we study the effect of these considerations on these engines. In particular, we look at various remote procedure execution mechanisms and the efficiency and safety of these mechanisms. Finally, we present performance results of the active storage framework on a variety of applications.
    Mass Storage Systems and Technologies (MSST), 2012 IEEE 28th Symposium on; 01/2012
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    ABSTRACT: This paper presents the multiple quantum well channel spatial wavefunction switched FETs (SWS-FETs) configured to implement multi-bit static random access memory (SRAM) cells. A 2-bit SRAM cell consists of two back-to-back connected 4-channel SWS-FETs, where each SWS-FET serves as quaternary inverter. This architecture results in reduction of FET count by 75% and data interconnect density by 50%. The designed 2-bit SRAM cell is simulated using BSIM equivalent channel models (for 25nm FETs). In addition, the binary interface logic and conversion circuitry are designed to integrate the SWS-SRAM technology. Quantum simulations for Si/Ge and InGaAs-based SWS-FETs are also presented.
    Lester Eastman Conference on High Performance Devices (LEC), 2012; 01/2012
  • S. Karmakar, J.A. Chandy, F.C. Jain
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    ABSTRACT: The spatial wave-function switched field effect transistor (SWSFET) has two or three low band-gap quantum well channels that can conduct carrier flow from source to drain of the SWSFET. Because of this property, SWSFETs are useful to implement different multi-valued logic with reduced device count. In this work, we introduce the circuit model of a SWSFET and the design of a unipolar inverter where only one kind of charge carrier contributes to the current flow.
    Lester Eastman Conference on High Performance Devices (LEC), 2012; 01/2012
  • A. Thamarakuzhi, J.A. Chandy
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    ABSTRACT: High-performance computing is highly dependent on the communication network connecting the nodes. In this paper, we present a design and implementation of the 2-dilated flattened butterfly (2DFB) network topology, which provides nonblocking performance for relatively low cost overhead. The flattened butterfly is known to be a cost efficient topology for high-radix networks. Because of its inherent path diversity, it is able to provide comparable cost/performance with the folded-Clos network in adversarial traffic conditions. However, the flattened butterfly is a blocking network and this blocking behavior can degrade the performance of the network when all compute nodes are transmitting and receiving data at full bandwidth. 2DFB network exhibits nonblocking behavior which is a critical factor in deciding the quality of any high performance computing system network. We have implemented the network using the NetFPGA as the switching element and verified the nonblocking behavior of 2DFB. We also compare the performance of a 2DFB with other switching networks. We also show that the 2DFB topology can be used to build high speed switching systems with reduced cost.
    IEEE Latin America Transactions 08/2011; · 0.22 Impact Factor
  • J. Singaraju, J.A. Chandy
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    ABSTRACT: We present an approach to perform transformation and reduction data operations in an intelligent network switch comprised of FPGAs. Data processing in a distributed system often requires the data to be aggregated at a single client before performing the data operation. Performing data processing in the interconnection network which has the global view of the data could speed up the application. In this paper, we show an example of a data sorting application that uses parallel servers to pre-sort data and then uses FPGAs within the switch to merge sort data as it passes through the network thereby reducing computation requirements at the client node. The architecture takes advantage of the NetFPGA board to perform a 4-way merge sort in an embedded network FPGA device. Using this architecture we show how data sort times can be reduced significantly.
    Reconfigurable Computing and FPGAs (ReConFig), 2010 International Conference on; 01/2011
  • Janardhan Singaraju, John A. Chandy
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    ABSTRACT: High performance computing systems are often inhibited by the performance of their storage systems and their ability to deliver data. Active Storage Networks (ASN) provide an opportunity to optimize storage system and computational performance by offloading computation to the network switch. An ASN is based around an intelligent network switch that allows data processing to occur on data as it flows through the storage area network from storage nodes to client nodes. In this paper, we demonstrate an ASN used to accelerate K-means clustering. The K-means data clusteringK-means\ data\ clustering algorithm is a compute intensive scientific data processing algorithm. It is an iterative algorithm that groups a large set of multidimensional data points in to k distinct clusters. We investigate functional and data parallelism techniques as applied to the K-means clustering problem and show that the in-network processing of an ASN greatly improves performance.
    Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings; 01/2011
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    ABSTRACT: Three-state behavior has been demonstrated in Si and InGaAs FETs when two layers of cladded nanodots (e.g. SiOx-cladded Si or GeOx-cladded Ge) are assembled on the thin tunnel gate insulator. The advantages of 3-state behavior in reducing device count in logic, analog-to-digital converters (ADCs), and DACs has been reported [1]. Unlike three-state QDG-FETs, four-state devices offer significant advantages in reducing device count and power dissipation in multi-valued logic architecture.
    01/2011;
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    Ajithkumar Thamarakuzhi, John A. Chandy
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    ABSTRACT: High-performance computing is highly dependent on the communication network connecting the nodes. In this paper, we propose a 2-Dilated flattened butterfly (2DFB) network which provides non-blocking performance for relatively low cost overhead. We study the topological properties of the proposed 2DFB network and compare it with different nonblocking switching topologies. We observe that a dilation factor of two is sufficient to obtain nonblocking property for a flattened butterfly structure irrespective of its size or dimension. Dilating each link in a flattened butterfly causes an increase in cost. Therefore, we modeled the implementation cost of a 2DFB network and compared it with other popular nonblocking networks. We observe that the cost of a 2DFB is less than other nonblocking networks, while at the same time providing reduced latency because of its reduced diameter and hop count. We also propose a procedure to develop a conflict-free static routing schedule as well as an adaptive load balanced routing scheme (ALDFB) for 2DFB networks. Finally, we also describe the hardware implementation of a 2DFB network using the NetFPGA as the switching element and verify the nonblocking behavior of a 2DFB. We also show that the 2DFB topology can be used to build high speed switching systems with reduced cost.
    Computer Communications - COMCOM. 01/2011; 34(15):1822-1835.
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    ABSTRACT: This paper presents the implementation of a novel InGaAs field-effect transistor (FET), using a ZnSe-ZnS-ZnMgS-ZnS stacked gate insulator, in a spatial wavefunction-switched (SWS) structural configuration. Unlike conventional FETs, SWS devices comprise two or more asymmetric coupled quantum wells (QWs). This feature enables carrier transfer vertically from one quantum well to another or laterally to the wells of adjacent SWS-FET devices by manipulation of the gate voltages (V g). Observation of an extra peak (near both accumulation and inversion regions) in the capacitance–voltage data in an InGaAs-AlInAs two-quantum-well SWS structure is presented as evidence of spatial switching. The peaks are attributed to the appearance of carriers first in the lower well and subsequently their transfer to the upper well as the gate voltage is increased. The electrical characteristics of a fabricated SWS InGaAs FET are also presented along with simulations of capacitance–voltage (C–V) behavior, showing the effect of wavefunction switching between wells. Finally, logic operations involving simultaneous processing of multiple bits in a device, using coded spatial location of carriers in quantum well channels, are also described. KeywordsInGaAs MOSFETs–spatial wavefunction-switched FETs–multibit processing
    Journal of Electronic Materials 01/2011; 40(8):1717-1726. · 1.64 Impact Factor