John A. Chandy

University of Connecticut, Storrs, Connecticut, United States

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Publications (70)24.91 Total impact

  • Supriya Karmakar, John A. Chandy, Faquir C. Jain
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 04/2015; 23(4):609-618. DOI:10.1109/TVLSI.2014.2320912 · 1.14 Impact Factor
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    ABSTRACT: Electron wavefunctions are switched spatially from one quantum well to another by varying the gate voltage V g in spatial wavefunction-switched (SWS) field-effect transistors (FETs), which comprise two or more coupled quantum wells serving as the transport channel. This is shown for Si/SiGe and InGaAs/AlInAs quantum well systems. The presence of charge in a particular well or channel is used to encode four states 00, 01, 10, 11. This unique property is used for two-bit processing, resulting in compact two-bit static random-access memory devices. Experimental data including capacitance-voltage peaks in Si and InGaAs multiple quantum well SWS-FETs has verified the SWS phenomenon. Replacing quantum wells by an array of cladded quantum dots, forming a quantum dot superlattice (QDSL) layer, enhances the contrast and noise margin in SWS-FETs. This paper reports I-V and C-V characteristics for a fabricated twin-drain SWS-quantum dot channel (QDC) FET comprising four layers of self-assembled SiO x -Si quantum dots. SWS-QDC-FETs are shown to be scalable to ∼9 nm, and comprise four layers of cladded quantum dots with an array of 3 × 3 forming the channel.
    Journal of Electronic Materials 01/2015; DOI:10.1007/s11664-015-3827-0 · 1.68 Impact Factor
  • Supriya Karmakar, John A. Chandy, Faquir C. Jain
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    ABSTRACT: A spatial wave-function switched field effect transistor (SWSFET) conducts current from the source to the drain region through different channels inside the FET based on the applied gate voltage. A circuit model of SWSFET is developed by modifying Berkeley short-channel IGFET model (BSIM 3.2.0), and a four-state inverter is designed based on that model. This four-state inverter may become a key element in future quaternary logic circuit design.
    12/2014; DOI:10.1080/00207217.2014.917718
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    ABSTRACT: High performance data processing clusters use parallelism to accelerate computation. Often, these computation processes require the transmission of data across networks. In this paper, we propose the use of computation within the network switch to perform computation on data on the fly and further accelerate computation. We call networks built with these compute switches Active Storage Networks (ASN) and they provide an opportunity to optimize storage system and computational performance by offloading some computation to the network switch. We present an approach to perform transformation and reduction data operations in a network switch comprised of FPGAs. In this paper, we demonstrate an ASN using representative data processing applications, namely data search, data sort, -min/max, and -means clustering.
    Future Generation Computer Systems 11/2014; 45. DOI:10.1016/j.future.2014.10.020 · 2.64 Impact Factor
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    ABSTRACT: Spatial wave-function switched field effect transistor (SWSFET) switches the current flow between different channels inside the FET based on the applied voltage in its gate terminal. SWSFET can be used to implement multi-valued logic circuit with less number of circuit elements. Recently we presented unipolar inverter circuit using SWSFET. In this paper we develop a circuit model of SWSFET based on BSIM 3.2.0 and BSIM 3.2.4 and implement membership function using that circuit model of SWSFET. The spatial wave-function switched field effect transistor (SWSFET) has two or three low band-gap quantum well channels inside the substrate of the semiconductor. Applied voltage at the gate region of the SWSFET, switches the charge carrier concentration in different channels from source to drain region. A circuit model of SWSFET is developed in BSIM 3.2.0. Membership function is implemented using the circuit model of the SWSFET. Membership function implementation using less number of SWSFET will reduce the device count in future analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuits.
    International Journal of High Speed Electronics and Systems 05/2014; 23(01n02). DOI:10.1142/S0129156414500074
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    ABSTRACT: In this paper, we are presenting fast digital to analog convertor designs using Spatial Waveform Switched FETs (SWSFET). SWSFET was introduced by Jain et.al. These FETs have multiple channels stacked vertically. The Carrier wavefunction switches from one channel to another with the application of different gate voltages. Designs of multi-bit SRAM, logic and sequential cells using SWSFETs have been demonstrated. Here we are introducing the use of SWSFET in mixed signal architectures. Single cycle architectures for two-bit, four-bit and eight-bit analog to digital converters are presented. Four bit architecture has been simulated and results are discussed. SWSFET presents the opportunity with its multiple stacked channel features to extend the Moors law using next generation of devices.
    International Journal of High Speed Electronics and Systems 05/2014; 23(01n02). DOI:10.1142/S0129156414500025
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    ABSTRACT: In this paper, we propose a new architecture for analog-to-digital converters (ADCs) using multistate spatial wavefunction-switched field-effect transistors (SWSFETs). SWSFETs are multiple quantum coupled well devices, where the wells are stacked vertically and the electron wavefunction switches from one well to another with the change in gate voltage. Quantum mechanical simulations of 3-well InGaAs-AlInAs SWSFET structures are presented. The designs and simulations of 2-bit and 3-bit ADCs using SWSFETs result in low power consumption and reduced device count which improves the speed of the data conversion.
    International Journal of High Speed Electronics and Systems 05/2014; 23(01n02). DOI:10.1142/S0129156414500050
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    ABSTRACT: Three-state behavior has been demonstrated in Si and InGaAs field-effect transistors (FETs) when two layers of cladded quantum dots (QDs), such as SiOx -cladded Si or GeOx -cladded Ge, are assembled on the thin tunnel gate insulator. This paper describes FET structures that have the potential to exhibit four states. These structures include: (1) quantum dot gate (QDG) FETs with dissimilar dot layers, (2) quantum dot channel (QDC) with and without QDG layers, (3) spatial wavefunction switched (SWS) FETs with multiple coupled quantum well channels, and (4) hybrid SWS–QDC structures having multiple drains/sources. Four-state FETs enable compact low-power novel multivalued logic and two-bit memory architectures. Furthermore, we show that the performance of these FETs can be enhanced by the incorporation of II–VI nearly lattice-matched layers in place of gate oxides and quantum well/dot barriers or claddings. Lattice-matched high-energy gap layers cause reduction in interface state density and control of threshold voltage variability, while providing a higher dielectric constant than SiO2. Simulations involving self-consistent solutions of the Poisson and Schrödinger equations, and transfer probability rate from channel (well or dot layer) to gate (QD layer) are used to design sub-12-nm FETs, which will aid the design of multibit logic and memory cells.
    Journal of Electronic Materials 11/2013; 42(11). DOI:10.1007/s11664-013-2758-x · 1.68 Impact Factor
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    ABSTRACT: This paper describes novel multibit static random-access memories (SRAMs) implemented using four-channel spatial wavefunction switched field-effect transistors (SWS FETs) with Ge quantum wells and ZnSSe barriers. A two-bit SRAM cell consists of two back-to-back connected four-channel SWS FETs, where each SWS FET serves as a quaternary inverter. This architecture results in a reduction of the field-effect transistor (FET) count by 75% and data interconnect density by 50%. The designed two-bit SRAM cell is simulated using Berkeley short-channel insulated-gate field-effect transistor equivalent-channel models (for 25-nm FETs). In addition, the binary interface logic and conversion circuitry are designed to integrate the SWS SRAM technology. Our motivation is to stack up multiple bits on a single SRAM cell without multiplying the transistor count. The concept of spatial wavefunction switching (SWS) in the FET structure has been verified experimentally for two- and four-well structures. Quantum simulations exhibiting SWS in four-well Ge SWS FET structures, using the ZnSe/ZnS/ZnMgS/ZnSe gate insulator, are presented. These structures offer higher contrast than Si-SiGe SWS FETs.
    Journal of Electronic Materials 11/2013; 42(11). DOI:10.1007/s11664-013-2762-1 · 1.68 Impact Factor
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    ABSTRACT: Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiOx -cladded Si or GeOx -cladded Ge quantum dots (QDs) with asymmetric dot sizes. An alternative method is to use both SiOx -cladded Si and GeOx -cladded Ge QDs in QDGFETs. In this paper, we present experimental verification of four-state behavior observed in a QDGFET with cladded Si and Ge dots site-specifically self-assembled in the gate region over a thin SiO2 tunnel layer on a Si substrate. This paper also investigates the use of lattice-matched high-κ ZnS-ZnMgS-ZnS layers as a gate insulator in mixed-dot Si QDGFETs. Quantum-mechanical simulation of the transfer characteristic (I D–V G) shows four-state behavior with two intermediate states between the conventional ON and OFF states.
    Journal of Electronic Materials 11/2013; 42(11). DOI:10.1007/s11664-013-2696-7 · 1.68 Impact Factor
  • Supriya Karmakar, John A. Chandy, Faquir C. Jain
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    ABSTRACT: This paper presents the implementation of six-bit analog to digital converters (ADCs) and digital-to-analog converters (DACs) using quantum dot gate non-volatile memory (QDNVM). The charge accumulation in the gate region varies the threshold voltage of QDNVM which can be used as a reference voltage source in a comparator circuit. A simplified comparator circuit can be implemented using the quantum dot gate non-volatile memory (QDNVM). In this work, we discuss the use of QDNVM based comparators in designing 6-bit Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs).
    Journal of Signal Processing Systems 06/2013; 75(3). DOI:10.1007/s11265-013-0789-4 · 0.56 Impact Factor
  • Supriya Karmakar, J.A. Chandy, F.C. Jain
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    ABSTRACT: In this paper, we discuss logic circuit designs using the circuit model of three-state quantum dot gate field effect transistors (QDGFETs). QDGFETs produce one intermediate state between the two normal stable ON and OFF states due to a change in the threshold voltage over this range. We have developed a simplified circuit model that accounts for this intermediate state. Interesting logic can be implemented using QDGFETs. In this paper, we discuss the designs of various two-input three-state QDGFET gates, including NAND- and NOR-like operations and their application in different combinational circuits like decoder, multiplier, adder, and so on. Increased number of states in three-state QDGFETs will increase the number of bit-handling capability of this device and will help us to handle more number of bits at a time with less circuit elements.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 05/2013; 21(5):793-806. DOI:10.1109/TVLSI.2012.2198248 · 1.14 Impact Factor
  • Orko Momin, John A. Chandy
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    ABSTRACT: In order to sustain scalability, clustered file systems distribute files across multiple I/O nodes in the cluster. The basis of many of these file systems is an object storage architecture where data is represented by variable sized containers called objects. The I/O nodes, however, use a POSIX file and directory interface which do not map well to the object interface. As a result, object storage nodes still have to resolve file paths and perform expensive lookup operations to find inodes and open objects stored as files. In this paper, we propose an alternative object based data interface where I/O node data can be accessed directly using object IDs instead of character strings. We modified an existing Linux file system to provide the object based interface which allows for faster data access times compared to the traditional directory-based interface. In addition, we modified a Object Storage Device (OSD) to use our object based interface to gain improvements in object creation and access. We believe this object based interface provides a useful alternative to the existing interface to provide better performance for cluster storage systems.
    Cluster Computing (CLUSTER), 2013 IEEE International Conference on; 01/2013
  • Cengiz Karakoyunlu, John A. Chandy
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    ABSTRACT: Object-Based Storage Devices (OSDs) offer an object-based data layout instead of using the traditional block-based design. Object storage ideas are increasingly being used in parallel file systems and cloud storage. Previous work has implemented the Parallel Virtual File System (PVFS) on OSDs by moving the metadata and data operations to the OSDs. In this paper, we present two new methods to further improve the performance of the existing PVFS-OSD implementation. These methods are using object collections to represent traditional directories on OSDs and delaying the creation of an OSD object until it is accessed by a write operation. The optimization methods are not particular to PVFS-OSD implementation and could be used with other parallel file systems-object storage implementations too. Experimental evaluations show that using collections yields up to 29 times of improvement in throughput; whereas delaying the creation of OSD objects provides 25% throughput improvement.
    Cluster Computing (CLUSTER), 2013 IEEE International Conference on; 01/2013
  • Ajithkumar Thamarakuzhi, John A. Chandy
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    ABSTRACT: The on-chip interconnection network (OCIN) and routing algorithms play an important role in the performance of a chip multiprocessor (CMP). As the number of cores in CMP increases, the OCIN also should scale efficiently to make use of the increasing processing capacity. An ideal OCIN should provide maximum throughput and minimum latency. We propose using a 2-dilated flattened butterfly (2DFB) instead of a mesh as a high- radix OCIN because of its non-blocking property and reduced diameter. We also present ALDFB, an adaptive load balanced routing scheme for 2DFB networks. We evaluate the performance of the 2DFB OCIN with ALDFB routing using synthetic traffic patterns and compare it with a mesh network having the samebisection bandwidth, which uses adaptive minimal routing scheme. We also compare the performance of ALDFB with two other most popular adaptive routing schemes. We observe that 2DFB with ALDFB provides significant improvement in terms of throughput and latency.
    Procedia Engineering 12/2012; 30:997-1004. DOI:10.1016/j.proeng.2012.01.956
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    ABSTRACT: This paper describes fabrication and modeling of quantum dot channel (QDC) field-effect transistors (FETs). A QDC-FET comprises an array of thin-barrier (~1 nm) cladded Si, Ge, or other quantum dots (3 nm to 4 nm) forming an n-channel on a p-Si layer/substrate between the source and drain regions. Experimental characteristics of fabricated QDC-FETs, consisting of two layers of cladded quantum dot arrays (e.g., SiOx -cladded Si dots and GeOx -cladded Ge dots) serving as the transport channel, are presented. Unlike conventional FETs, QDC-FET structures exhibit step-like I D–V G characteristics and discretely bunched I D–V D characteristics as a function of gate voltage. The transfer characteristics appear to be similar to those of single-electron transistors (SETs). However, QDC-FETs employ transport of many electrons and operate at room temperature. A one-dimensional Tsu–Esaki equation is used to simulate the quantum dot channel and explain the steps in the current–voltage behavior. In particular, the effect of the II–VI barrier layers on Ge dots is modeled. The QDC-FET channel is also modeled as having superlattice-like mini-energy bands whose bandwidth and separation are determined by the dot size, cladding thickness, and barrier height. For a given gate voltage (which determines the carrier concentration), carriers in the inversion channel are transported via mini-energy bands that line up with the Fermi level as the drain voltage V DS is changed, producing step-like multistate electrical characteristics. Formation of the quantum dot channel enables higher-mobility transport on very low-mobility substrates or thin films such as poly-Si. The channel mobility can be further enhanced by partially removing the oxide barrier layer and replacing it with lattice-matched II–VI gate insulator layers.
    Journal of Electronic Materials 10/2012; 41(10). DOI:10.1007/s11664-012-2161-z · 1.68 Impact Factor
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    ABSTRACT: This paper presents the fabrication of a negative-channel metal–oxide–semiconductor (NMOS) inverter based on quantum dot gate field-effect transistors (QDG-FETs). A QDG-FET produces one intermediate state in its transfer characteristic. NMOS inverters based on a QDG-FET produce three states in their transfer characteristic. The generation of the third state in the inverter characteristic makes this a promising circuit element for multivalued logic implementation. A circuit simulation result based on the Berkley simulation (BSIM) circuit model of the QDG-FET is also presented in this paper, predicting the fabricated device characteristic.
    Journal of Electronic Materials 08/2012; 41(8). DOI:10.1007/s11664-012-2116-4 · 1.68 Impact Factor
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    ABSTRACT: Spatial Wavefunction-Switched (SWS) Field-Effect Transistors (FETs) consist of inversion layers comprising two or more coupled quantum wells (QWs). Carriers can be localized in any of the wells and vertically transferred between them by changing the gate voltage. In addition, carriers can also be laterally transferred between adjacent SWSFET devices by the manipulation of the gate voltages (Vg). This enables processing of two more bits simultaneously by changing the spatial location of the carrier ensemble wavefunction, which in turn determines the state of the device [e.g., electrons in well W2 (01), in W1 (10), in both (11), in neither (00)]. Experimentally, the capacitance-voltage data, having a distinct peak, has been presented in InGaAs-AlInAs two-quantum well structures. The peak(s) are attributed to the appearance of carriers, first in the lower well and subsequently their transfer to the upper well. Use of multiple channels allows for CMOS-like configuration with both transistors having n-channel mobilities. Simulation of an InGaAs SWS inverter computes a gate delay of 0.24ps. A cut-off frequency in excess of 8THz is computed for 12nm channel length InGaAs SWSFETs. Examples, including logic gates and a 3-bit full-adder, are presented to show the reduction of device count when SWS-FETs are employed.
    International Journal of High Speed Electronics and Systems 04/2012; 20(03). DOI:10.1142/S0129156411006933
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    ABSTRACT: Three-state behavior has been demonstrated in Si and InGaAs quantum dot gate (QDG) field-effect transistorsootnotetextS. Karmakar, et al., J. Electronic Materials, 40, 1746, 2011.^,ootnotetextF Jain, J. Electronic Materials, 40, 1717, 2011. (FETs). Recently, spatial wavefunction switchedootnotetextIbid. (SWS) and quantum dot channelootnotetextF. Jain et al., Proc. II-VI Workshop, Oct.2011. (QDC) FETs have been reported to exhibit four-state operation. This paper presents simulations of versatile combinations of SWS features in QDC channels to optimally design multi-state transport in FETs that have the potential of scaling to sub-12nm regime. A QDC-FET channel is modeled as having superlattice-like mini-energy bands where the carrier wavefunctions are transferred across the channel as drain voltage is changed, producing step-like multi-state electrical characteristics. This behavior is analogous to that of single electron transistors.ootnotetextS. J. Shin, et al., Appl. Phys. Lett. 97, 103101, 2010. The difference is that QDC devices use more than a few electrons and operate at room temperature. The SWS feature additionally provides carrier transfer from lower to upper dot layer(s) in a QDC having more than one layer of quantum dots.