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ABSTRACT: A versatile 30V analog CMOS process in a 0.18 μm technology node has been developed by using cost-effective and modular fashion. To reduce the thermal budget deep NWELL isolation is formed after CMOS well formation. The drain-extended (DE) CMOS from 7V to 30V shows very competitive trade-off performance between the breakdown voltage and the specific on-resistance. In addition, low 1/f noise of 5V CMOS can be obtained by pure gate oxide process.
Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on; 06/2011
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Kwang-Young Ko,
Il-Yong Park,
Yong-Keon Choi,
Chul-Jin Yoon,
Ju-Hyoung Moon,
Kyung-Min Park,
Hyon-Chol Lim,
Soon-Yeol Park, Nam-Joo Kim,
Kwang-Dong Yoo,
L.N. Hutter
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ABSTRACT: 0.18μm BCD technology with the best-in-class nLDMOS is presented. The drift of nLDMOS is optimized to ensure lowest Rsp by using multi-implants and appropriate thermal recipe. The optimized 24V nLDMOS has BV<sub>DSS</sub>=36V and Rsp=14.5 mΩ-mm<sup>2</sup>. Electrical SOA and long-term hot electron (HE) SOA are also evaluated. The maximum operating voltage less than 10% degradation of on-resistance is 24.4V.
Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on; 07/2010
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Choul-Joo Ko,
Cheol-Ho Cho,
Hee-Bae Lee,
Yong-Jun Lee,
Min-Woo Kim,
Sun-Kyung Bang,
Han-Geon Kim,
Jae-O Lee,
Sang-Chul Shim,
Sun Kyoung Kang, Nam-Joo Kim,
Kwang-Dong Yoo,
L.N. Hutter
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ABSTRACT: We present a new 0.35um BCDMOS technology with a capability of 8 to 60V NLDMOS. The proposed process do not need level shifter, charge pump and boost up due to the same gate oxide thickness with logic 5V CMOS. And the Rsp of the proposed 24V NLDMOS structure is lower by 46% than conventional structure. The process has no thermal budget modification but use simple additional implant step. Also it is compatible with the conventional BCDMOS. The power LDMOS transistors in the process have very competitive performances with NLDMOS in 0.15 - 0.25um BCDMOS technologies.
Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on; 07/2010
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ABSTRACT: We experimentally demonstrate a super-junction LDMOS transistor in a 0.18 mum BCD technology. The buffered super-junction structure is implemented by the use of existing N- and P-drift layer, which are optimized for conventional 20 V to 30 V LDMOS transistors. The breakdown voltage and the specific on-resistance of the fabricated super-junction LDMOS are 98.6 V and 1.01 mOmegaldrcm<sup>2</sup>, respectively. The TLP measurement results show fairly good electrical SOA characteristics up to 78 V for all gate voltages.
Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on; 07/2009
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ABSTRACT: This paper report 85 V high-side LDMOS which is implemented in a conventional 0.3 5 um BCDMOS process using one additional mask. The process has no thermal budget modification but use simple additional implant step. Also it is completely compatible with the conventional BCDMOS process and has similar performances with 80 V SOI LDMOS.
Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th International Symposium on; 06/2008
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ABSTRACT: We present a new BCD technology in a 0.18 μm technology platforms with a capability of 7 to 60V high-voltage devices such as DEMOS and LDMOS. The developed 0.18 mum BCD process provides various kinds of high voltage LDMOS such as 7, 12, 20, 50, 60 V LDMOS transistors for variety of applications. The power LDMOS transistors in the process have very competitive specific on-resistance compared to previous results.
Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th International Symposium on; 06/2008
