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ABSTRACT: Experimental data from undoped-body gate-all-around (GAA) silicon nanowire (NW) MOSFETs with different sizes demonstrate the universality of short-channel effects as a function of L <sub>EFF</sub>/λ, where L <sub>EFF</sub> is the effective channel length and λ is the electrostatic scaling length. Data from undoped-body single-gate extremely thin SOI (ETSOI) devices additionally show that the universality of short-channel effects is valid for any undoped-body fully depleted SOI MOSFET. Our data indicate that L <sub>EFF</sub> of undoped GAA NW MOSFETs can be scaled down by ~2.5 times compared with undoped single-gate ETSOI MOSFETs while maintaining equivalent short-channel control.
IEEE Electron Device Letters 10/2010; · 2.85 Impact Factor
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ABSTRACT: We present a study of the effects of substrate orientation and longitudinal channel stress on the performance of extremely thin silicon-on-insulator (ETSOI) MOSFETs with gate lengths down to 25 nm. We find that short-channel electron and hole mobilities follow the long-channel mobility trends versus substrate orientation and longitudinal channel stress. We show that with respect to (100) silicon-on-insulator (SOI) substrates, short-channel ETSOI MOSFETs on (110) SOI substrates lead to 25% enhancement of the p-channel FET drive current at the expense of 12% degradation of the n-channel FET drive current at a fixed off-current of 100 nA/μm and a supply voltage of 1 V. Finally, we estimate that an ETSOI complementary metal-oxide-semiconductor (CMOS) on (110) SOI substrates should lead to 10% faster ring oscillators compared with those on (100) SOI wafers, which also implies that (100)-oriented wafers with (110) sidewalls are a better choice for fabricating nonplanar FinFETs and trigate CMOS circuits.
IEEE Transactions on Electron Devices 10/2010; · 2.32 Impact Factor
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ABSTRACT: We present a detailed study of gate length scalability and device performance of undoped-body extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates. We show that short channel control improves with the application of back bias via a decrease in the electrostatic scaling length as the subthreshold charges move toward the front gate. We demonstrate that, even for undoped ETSOI devices with ~8-nm SOI thickness, the improvement in short channel control with the application of a back bias translates to 10% higher drive current, 10% shorter gate lengths, and, consequently, 20% lower extrinsic gate delay at a fixed off-state current of 100 nA/mum and a back oxide electric field of 1.5 MV/cm (0.5 MV/cm SOI field).
IEEE Transactions on Electron Devices 11/2009; · 2.32 Impact Factor
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ABSTRACT: In this letter, we show that undoped-body extremely thin SOI (ETSOI) MOSFETs with SOI thickness in the 4-6-nm range have excellent short-channel control down to 20-25-nm gate lengths, suitable for the 22-nm technology node and beyond. We demonstrate that 6-nm-thin ETSOI devices can deliver high drive currents required for logic applications. Finally, we bring to fore the need for improvements in etch and doping processes to reduce series resistance of 4-nm-thin ETSOI devices in order to make them a viable option for the 15-nm technology node.
IEEE Electron Device Letters 05/2009; · 2.85 Impact Factor
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ABSTRACT: We have fabricated undoped-body short-channel extremely thin silicon-on-insulator (ETSOI) field-effect transistors (FETs) with 8-nm SOI thickness that exhibit the expected short-channel benefit compared with doped partially depleted SOI (PDSOI) FETs. Using a source/drain extension (SDE) last process with the SDE implants activated with diffusionless laser anneal, we demonstrate that the series resistance penalty can be minimized, which leads to ETSOI FET drive currents that are comparable to those of conventional thick-body PDSOI FETs.
IEEE Electron Device Letters 06/2008; · 2.85 Impact Factor
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ABSTRACT: We report 65 nm ground-rule, partially depleted, low-power silicon-on-insulator (LPSOI) CMOS devices with total leakage current /<sub>Off</sub> down to 10 pA / mum at supply voltage V <sub>DD</sub> = 1.2 V. NFET / PFET drive current I<sub>DSAT</sub> = 550/250 muA /mum at /off = 100 pA/mum and gate length L<sub>G</sub> ~ 55 nm are achieved with a single tensile liner film. Innovative junction engineering techniques such as low-damage junction pre- amorphization implants (PAI), source-side high-damage PAI, high-energy halo, and drain-side tilted source/drain (S/D) implants are evaluated for their effectiveness in minimizing SOI floating body effect for low leakage design. Our result suggests that there is no fundamental limit for low leakage application of SOI.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
