Lan Wei

Massachusetts Institute of Technology, Cambridge, Massachusetts, United States

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Publications (27)16.97 Total impact

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    ABSTRACT: A semianalytical carbon nanotube field-effect transistor (CNFET) model based on the virtual-source model is presented, which includes series resistance, parasitic capacitance, and direct source-to-drain tunneling leakage. The model is calibrated with recent experimental data down to 9-nm gate length. Device performance of 22- to 7-nm technology nodes is analyzed. The results suggest that contact resistance is the key performance limiter for CNFETs; direct source-to-drain tunneling results in significant leakage due to low effective mass in carbon nanotubes and prevents further downscaling of the gate length. The design space that minimizes the gate delay in CNFETs subject to OFF-state leakage current (IOFF) constraints is explored. Through the optimization of the length of the gate, contact, and extension regions to balance the parasitic effects, the gate delay can be improved by more than 10% at 11- and 7-nm technology nodes compared with the conventional 0.7 × scaling rule, while the OFF-state leakage current remains below 0.5 μA/μm .
    IEEE Transactions on Electron Devices 06/2013; 60(6):1834-1843. DOI:10.1109/TED.2013.2258023 · 2.36 Impact Factor
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    ABSTRACT: A statistical extension of the ultra-compact Virtual Source (VS) MOSFET model is developed here for the first time. The characterization uses a statistical extraction technique based on the backward propagation of variance (BPV) with variability parameters derived directly from the nominal VS model. The resulting statistical VS model is extensively validated using Monte Carlo simulations, and the statistical distributions of several figures of merit for logic and memory cells are compared with those of a BSIM model from a 40-nm CMOS industrial design kit. The comparisons show almost identical distributions with distinct run time advantages for the statistical VS model. Additional simulations show that the statistical VS model accurately captures non-Gaussian features that are important for low-power designs.
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013; 01/2013
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    ABSTRACT: In this paper, we present the first validation of the virtual source (VS) charge-based compact model for standard cell libraries and large-scale digital circuits. With only a modest number of physically meaningful parameters, the VS model accounts for the main short-channel effects in nanometer technologies. Using a novel DC and transient parameter extraction methodology, the model is verified with simulated data from a well-characterized, industrial 40-nm bulk silicon model. The VS model is used to fully characterize a standard cell library with timing comparisons showing less than 2.7% error with respect to the industrial design kit. Furthermore, a 1001-stage inverter chain and a 32-bit ripple-carry adder are employed as test cases in a vendor CAD environment to validate the use of the VS model for large-scale digital circuit applications. Parametric Vdd sweeps show that the VS model is also ready for usage in low-power design methodologies. Finally, runtime comparisons have shown that the use of the VS model results in a speedup of about 7.6×.
    Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific; 01/2013
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    ABSTRACT: Compact modeling of resistive switching memory (RRAM) and carbon nanotube field-effect transistor (CNFET) are presented. The models are suitable for exploration of device design space, assessment of device performance at the circuit level. Optimization of the CNFET device structure to minimize the gate delay is presented as a demonstration of the model's capability. Simulation of neuromorphic computation system is an example application of the RRAM model. The models can be used to perform advance explorations of circuits and sub-systems of emerging devices prior to the availability of reliable, high-yielding fabrication processes for the emerging devices.
    Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of; 01/2013
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    ABSTRACT: A simple analytical FET channel charge partitioning model valid under ballistic and quasi-ballistic transport conditions is developed. With this model, the virtual-source (VS) based charge-based transport compact model is extended to include self-consistent analytical channel charge partitioning models for quasi- and fully-ballistic conditions, with continuous current and charges and their derivatives. Drift–diffusion with or without velocity-saturation transport conditions are also comprehended with adaptations of existing-literature models, and the resulting terminal charges and capacitances are compared with those assuming ballistic operation. With only a limited number of physically meaningful parameters, the extended VS compact model forms an ideal platform for the exploration of the dynamic behavior of current and future FET devices. The simple model is validated here by comparison with experimental data from a well-characterized industry 45-nm metal/high- $k$ complementary metal–oxide–semiconductor including parasitic elements using a Verilog-A implementation to simulate ring oscillators. It is also validated by comparison with S-parameter-derived capacitances of near-ballistic III–V high-electron mobility transistors. In both cases, the effects of different assumed transport conditions on the dynamic device behavior are explored.
    IEEE Transactions on Electron Devices 05/2012; 59(5):1263-1271. DOI:10.1109/TED.2012.2186968 · 2.36 Impact Factor
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    ABSTRACT: Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly energy-efficient electronic systems of the future. Fundamental limitations inherent to carbon nanotubes (CNTs) pose major obstacles to the realization of robust CNFET digital very large-scale integration (VLSI): 1) it is nearly impossible to guarantee perfect alignment and positioning of all CNTs despite near-perfect CNT alignment achieved in recent years; 2) CNTs can be metallic or semiconducting depending on chirality; and 3) CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. Today's CNT process improvements alone are inadequate to overcome these challenges. This paper presents an overview of: 1) imperfections and variations inherent to CNTs; 2) design and processing techniques, together with a probabilistic analysis framework, for robust CNFET digital VLSI circuits immune to inherent CNT imperfections and variations; and 3) recent experimental demonstration of CNFET digital circuits that are immune to CNT imperfections. Significant advances in design tools can enable robust and scalable CNFET circuits that overcome the challenges of the CNFET technology while retaining its energy-efficiency benefits.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 04/2012; 31(4):453-471. DOI:10.1109/TCAD.2012.2187527 · 1.20 Impact Factor
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    ABSTRACT: Recent advances in nanophotonic device research have led to a proliferation of proposals for new architectures that employ optics for on-chip communication. However, since standard simulation tools have not yet caught up with these advances, the quality and thoroughness of the evaluations of these architectures have varied widely. This paper provides the first complete end-to-end analysis of an architecture using on-chip optical interconnect. This analysis incorporates realistic performance and energy models for both electrical and optical devices and circuits into a full-fledged functional simulator, thus enabling detailed analyses when running actual applications. Since on-chip optics is not yet mature and unlikely to see widespread use for several more years, we perform our analysis on a future 1000-core processor implemented in an 11nm technology node. We find that the proposed optical interconnect can provide between 1.8x and 4.8x better energy-delay product than conventional electrical-only interconnects. In addition, based on a detailed energy breakdown of all processor components, we conclude that a thermal ring resonators and on-chip lasers that allow rapid power gating are key areas worthy of additional nanophotonic research. This will help guide future optical device research to the areas likely to provide the best payoff.
    Parallel & Distributed Processing Symposium (IPDPS), 2012 IEEE 26th International; 01/2012
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    ABSTRACT: A physics-based compact transport and charge model for GaN HEMTs has been developed. The model includes effects such as self-heating, non-linear access region behavior, electron-phonon interaction etc. The model is validated against fabricated devices and is used to evaluate fT improvements in short channel devices. The model is also a suitable base for GaN FET circuit simulation compact models.
    Electron Devices Meeting (IEDM), 2012 IEEE International; 01/2012
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    ABSTRACT: With the rise of many-core chips that require substantial bandwidth from the network on chip (NoC), integrated photonic links have been investigated as a promising alternative to traditional electrical interconnects. While numerous opto-electronic NoCs have been proposed, evaluations of photonic architectures have thus-far had to use a number of simplifications, reflecting the need for a modeling tool that accurately captures the tradeoffs for the emerging technology and its impacts on the overall network. In this paper, we present DSENT, a NoC modeling tool for rapid design space exploration of electrical and opto-electrical networks. We explain our modeling framework and perform an energy-driven case study, focusing on electrical technology scaling, photonic parameters, and thermal tuning. Our results show the implications of different technology scenarios and, in particular, the need to reduce laser and thermal tuning power in a photonic network due to their non-data-dependent nature.
    Networks on Chip (NoCS), 2012 Sixth IEEE/ACM International Symposium on; 01/2012
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    ABSTRACT: In this paper, an analytical model of intrinsic carbon-nanotube field-effect transistors is presented. The origins of the channel carriers are analyzed in the ballistic limit. A noniterative surface-potential model is developed based on an analytical electrostatic model and a piecewise constant quantum-capacitance model. The model is computationally efficient with no iteration or numerical integration involved, thus facilitating fast circuit simulation and system optimization. Essential physics such as drain-induced barrier lowering and quantum capacitance are captured with reasonable accuracy.
    IEEE Transactions on Electron Devices 09/2011; 58(8-58):2456 - 2465. DOI:10.1109/TED.2011.2153858 · 2.36 Impact Factor
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    ABSTRACT: Historically, the off-state current I <sub>off</sub> and the supply voltage Vdd are specified as technology targets for Si metal-oxide-semiconductor field-effect transistors (MOSFETs) at each technology node. Emerging device technologies such as III-V transistors, carbon-nanotube FETs (CNFETs), and tunneling FETs (TFETs) are often targeted to outperform Si MOSFETs at the same I <sub>off</sub> and Vdd values. However, the conclusions from the conventional methodology are limited for advanced technology and diversified applications, when Dennard scaling is inefficient and different device structures are invented. We present a new device-technology assessment methodology based on energy-delay optimization, which takes into consideration key circuit-level information, such as logic depth, activity factors, and fanout (FO). Our methodology starts from device I - V and C - V characteristics and treat I <sub>off</sub> and Vdd as “free variables.” Together with device and supply-voltage variations, we obtain a corresponding and different optimal set of I <sub>off</sub> and Vdd and optimal energy-delay for each emerging device. We show that today's best available III-V transistors and CNFETs can outperform the best Si FETs by 1.5-2 and 2-3.5 times in terms of energy efficiency, respectively. Projected into the 10-nm-gate-length regime, III-V-on-insulator, CNFETs, and TFETs are 1.25, 2-3, and 5-10 times better than the International Technology Roadmap for Semiconductors target, for FO1 delays of 0.3, 0.1, and 1 ns, respectively.
    IEEE Transactions on Electron Devices 09/2011; 58(8-58):2430 - 2439. DOI:10.1109/TED.2011.2157349 · 2.36 Impact Factor
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    ABSTRACT: Parasitic capacitances have become a main issue for advanced technology nodes. In this paper, we develop analytical models for parasitic capacitance components for several device structures, including bulk devices, fully depleted silicon-on-insulator devices, and double-gate devices. With these models, we analyze the impact of parasitic capacitances on the circuit-level performance for logic applications. Si complementary metal-oxide-semiconductor roadmap projection is revisited beyond 32-nm technology, with different device design scenarios examined.
    IEEE Transactions on Electron Devices 06/2011; 58(5-58):1361 - 1370. DOI:10.1109/TED.2011.2121912 · 2.36 Impact Factor
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    ABSTRACT: Summary form only given. Miniaturization of device feature size has improved both device density and device performance in the conventional scaling era. However, degradation of electrostatic gate control, increasing contribution of parasitics, and increasing power consumption have limited scalability. The slow-down of L<sub>g</sub> scaling has been compensated for by technology features such as strain engineering, high-κ dielectric, and novel channel materials and device structures. Looking forward, new trends for device design are expected. Particularly, considerable amount of attention is needed in 1) parasitics, and 2) understanding device design and its impact on the circuit-level environment. For advanced technologies and emerging devices, technology development and device design has to be revisited, as conventional methods of performance benchmarking are unable to capture the system-level power-constrained circuit design tradeoffs. In this paper, several issues on technology development are further addressed based on the study of device and circuit interactive design and optimization.
    Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2011
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    ABSTRACT: Aspiring emerging device technologies (e.g. III-V, CNFET, TFET) are often targeted to outperform Si FETs at the same off-state current (I<sub>off</sub>) and supply voltage (V<sub>dd</sub>). We present a new device technology assessment methodology based on energy-delay optimization which treats I<sub>off</sub> and V<sub>dd</sub> as “free variables”, and bounded by constraints due to device variation and circuit noise margin. We show that for each emerging device (III-V, CNFET, TFET), there is a corresponding and different optimal set of I<sub>off</sub> and V<sub>dd</sub>, and an optimal energy-delay. Today's best-available III-V and CNFET can outperform the best Si FET by 1.5-2x and 2-3.5x, respectively. Projected into the 10nm gate length regime, III-V on-Insulator, CNFET, and TFET are 1.25x, 2-3x, and 5-10x (for FO1 delays of 0.3ns, 0.1ns, and 1ns respectively) better than the ITRS target at the same gate length.
    Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2011
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    ABSTRACT: Meeting reliability requirements is an increasingly more difficult challenge with each generation of CMOS technology. The disconnection between conventional one-size-fits-all reliability specifications and the wide range of circuit applications might be a huge waste of resources. By taking into consideration circuit- level figures of merit, a novel methodology to establish device reliability criteria that reflects real-world operation of devices in circuits is proposed and demonstrated. This "circuit-aware" methodology makes a real step toward realizing the goal of application-aware reliability standards which do not require additional measurements. The beauty is its simplicity - a simple transformation to solve an important problem. The simplicity makes it attractive as a standard methodology. I. INTRODUCTION A critical aspect of qualifying VLSI technology for full scale production is satisfying reliability criteria. As CMOS technology continues to advance, it is becoming increasingly more difficult for a new technology to meet all of its reliability specifications. Additionally, many of the reliability qualification specifications are based on seemingly arbitrary device parametric shifts and do not necessarily correlate with real world circuit behavior; product reliability in the field often shows no correlation with the qualification criteria. The current standard of a single device-level reliability specification, which is used to qualify all circuit applications for a particular technology, is illogical, wasteful, and painful. It makes little sense to universally trade performance for reliability or vice-versa regardless of the circuit application. Thus, there is a real and urgent need to develop reliability criteria that can reflect a particular circuit's actual application
    Proceedings of the 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, Sept. 12-16, 2011; 01/2011
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    ABSTRACT: Currently, technology innovations focus on enhancing carrier transport properties by introducing novel materials (e.g. III–V and Ge) and improving short channel electrostatic control by adopting novel structures (e.g. multi-gate). In this paper, we show that the performance benefits at the circuit-level depend strongly on the target applications and load scenarios. Enhanced electrostatic control improves circuit-level energy-delay trade-off for both high-performance (HP) and low-power (LP) applications, while better transport only benefits the HP application. To achieve the optimal energy-delay trade-off at the circuit-level, P/N width ratio, supply voltage (Vdd), and width-normalized off-state current (Ioff) must be optimized for the target application and load scenario.
    Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International 01/2011; DOI:10.1109/IEDM.2011.6131558
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    ABSTRACT: By surmounting various obstacles across the spectrum from material synthesis to device fabrication and circuit considerations, we provide a solid foundation so that carbon-based technology can move forward towards the vision of engineering VLSI circuits, but further research is still needed to realize the material potential such as higher density CNT synthesis, better metal to CNT/graphene contacts, and air-stable doping of CNT.
    International Symposium on VLSI Technology, Systems, and Applications, Proceedings 01/2011; DOI:10.1109/VTSA.2011.5872209
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    ABSTRACT: Carbon Nanotube Field-Effect Transistors (CNFETs) are excellent candidates for designing highly energy-efficient future digital systems. However, carbon nanotubes (CNTs) are inherently highly subject to imperfections that pose major obstacles to robust CNFET digital VLSI. This paper summarizes commonly raised questions and concerns about CNFET technology through a series of frequently asked questions. The specific questions addressed in this paper are motivated by recent advances in the field since the publication of our earlier paper on frequently asked questions in the Proceedings of the 2009 Design Automation Conference.
    2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, November 7-10, 2011; 01/2011
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    ABSTRACT: Because of high carrier velocities and quasi-ballistic transport properties, carbon-based (nanotube, graphene) field effect transistors (CNFETs) are considered to be potential candidates to replace CMOS in future technology generations . Most prior modeling of CNFETs has involved complex models, such as NEGF , but to properly evaluate these devices in circuits and systems, efficient compact models are required. In this paper, a fully analytical model based on ballistic transport and careful analysis of quantum capacitances is developed. This model requires neither iteration nor numeric integration. The model agrees well with numerical simulation and, in the limit of good contacts, predicts that a new effect, source exhaustion (using up all available carriers in the source), should limit the current. The model has also been integrated into a system level design optimization program which evaluates optimal device parameters based on system-level design objectives. The CNFET is projected to achieve 5× chip-level speed up over PDSOI at 11 nm technology node for a high-performance four-core processor with 1.5M logic gates.
    Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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    ABSTRACT: We review recent efforts to capture the device nonidealities for circuit-level technology projection for Si CMOS. We also give some examples of simple compact model development for assessing the circuit-level performance of exploratory devices such as III-V FET, carbon nanotube transistor, and nanoelectromechanical (NEM) transistors and relays.
    Simulation of Semiconductor Processes and Devices, 2009. SISPAD '09. International Conference on; 10/2009