Lan Wei

Massachusetts Institute of Technology, Cambridge, Massachusetts, United States

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Publications (20)13.2 Total impact

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    ABSTRACT: A semianalytical carbon nanotube field-effect transistor (CNFET) model based on the virtual-source model is presented, which includes series resistance, parasitic capacitance, and direct source-to-drain tunneling leakage. The model is calibrated with recent experimental data down to 9-nm gate length. Device performance of 22- to 7-nm technology nodes is analyzed. The results suggest that contact resistance is the key performance limiter for CNFETs; direct source-to-drain tunneling results in significant leakage due to low effective mass in carbon nanotubes and prevents further downscaling of the gate length. The design space that minimizes the gate delay in CNFETs subject to OFF-state leakage current (IOFF) constraints is explored. Through the optimization of the length of the gate, contact, and extension regions to balance the parasitic effects, the gate delay can be improved by more than 10% at 11- and 7-nm technology nodes compared with the conventional 0.7 × scaling rule, while the OFF-state leakage current remains below 0.5 μA/μm .
    IEEE Transactions on Electron Devices 06/2013; 60(6):1834-1843. · 2.06 Impact Factor
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    ABSTRACT: Compact modeling of resistive switching memory (RRAM) and carbon nanotube field-effect transistor (CNFET) are presented. The models are suitable for exploration of device design space, assessment of device performance at the circuit level. Optimization of the CNFET device structure to minimize the gate delay is presented as a demonstration of the model's capability. Simulation of neuromorphic computation system is an example application of the RRAM model. The models can be used to perform advance explorations of circuits and sub-systems of emerging devices prior to the availability of reliable, high-yielding fabrication processes for the emerging devices.
    Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of; 01/2013
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    ABSTRACT: Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly energy-efficient electronic systems of the future. Fundamental limitations inherent to carbon nanotubes (CNTs) pose major obstacles to the realization of robust CNFET digital very large-scale integration (VLSI): 1) it is nearly impossible to guarantee perfect alignment and positioning of all CNTs despite near-perfect CNT alignment achieved in recent years; 2) CNTs can be metallic or semiconducting depending on chirality; and 3) CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. Today's CNT process improvements alone are inadequate to overcome these challenges. This paper presents an overview of: 1) imperfections and variations inherent to CNTs; 2) design and processing techniques, together with a probabilistic analysis framework, for robust CNFET digital VLSI circuits immune to inherent CNT imperfections and variations; and 3) recent experimental demonstration of CNFET digital circuits that are immune to CNT imperfections. Significant advances in design tools can enable robust and scalable CNFET circuits that overcome the challenges of the CNFET technology while retaining its energy-efficiency benefits.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 01/2012; 31(4):453-471. · 1.09 Impact Factor
  • Lan Wei, S. Oh, H.-S.P. Wong
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    ABSTRACT: Historically, the off-state current I <sub>off</sub> and the supply voltage Vdd are specified as technology targets for Si metal-oxide-semiconductor field-effect transistors (MOSFETs) at each technology node. Emerging device technologies such as III-V transistors, carbon-nanotube FETs (CNFETs), and tunneling FETs (TFETs) are often targeted to outperform Si MOSFETs at the same I <sub>off</sub> and Vdd values. However, the conclusions from the conventional methodology are limited for advanced technology and diversified applications, when Dennard scaling is inefficient and different device structures are invented. We present a new device-technology assessment methodology based on energy-delay optimization, which takes into consideration key circuit-level information, such as logic depth, activity factors, and fanout (FO). Our methodology starts from device I - V and C - V characteristics and treat I <sub>off</sub> and Vdd as “free variables.” Together with device and supply-voltage variations, we obtain a corresponding and different optimal set of I <sub>off</sub> and Vdd and optimal energy-delay for each emerging device. We show that today's best available III-V transistors and CNFETs can outperform the best Si FETs by 1.5-2 and 2-3.5 times in terms of energy efficiency, respectively. Projected into the 10-nm-gate-length regime, III-V-on-insulator, CNFETs, and TFETs are 1.25, 2-3, and 5-10 times better than the International Technology Roadmap for Semiconductors target, for FO1 delays of 0.3, 0.1, and 1 ns, respectively.
    IEEE Transactions on Electron Devices 09/2011; · 2.06 Impact Factor
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    ABSTRACT: In this paper, an analytical model of intrinsic carbon-nanotube field-effect transistors is presented. The origins of the channel carriers are analyzed in the ballistic limit. A noniterative surface-potential model is developed based on an analytical electrostatic model and a piecewise constant quantum-capacitance model. The model is computationally efficient with no iteration or numerical integration involved, thus facilitating fast circuit simulation and system optimization. Essential physics such as drain-induced barrier lowering and quantum capacitance are captured with reasonable accuracy.
    IEEE Transactions on Electron Devices 09/2011; · 2.06 Impact Factor
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    ABSTRACT: Parasitic capacitances have become a main issue for advanced technology nodes. In this paper, we develop analytical models for parasitic capacitance components for several device structures, including bulk devices, fully depleted silicon-on-insulator devices, and double-gate devices. With these models, we analyze the impact of parasitic capacitances on the circuit-level performance for logic applications. Si complementary metal-oxide-semiconductor roadmap projection is revisited beyond 32-nm technology, with different device design scenarios examined.
    IEEE Transactions on Electron Devices 06/2011; · 2.06 Impact Factor
  • Lan Wei, S. Oh, H.-S.P. Wong
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    ABSTRACT: Aspiring emerging device technologies (e.g. III-V, CNFET, TFET) are often targeted to outperform Si FETs at the same off-state current (I<sub>off</sub>) and supply voltage (V<sub>dd</sub>). We present a new device technology assessment methodology based on energy-delay optimization which treats I<sub>off</sub> and V<sub>dd</sub> as “free variables”, and bounded by constraints due to device variation and circuit noise margin. We show that for each emerging device (III-V, CNFET, TFET), there is a corresponding and different optimal set of I<sub>off</sub> and V<sub>dd</sub>, and an optimal energy-delay. Today's best-available III-V and CNFET can outperform the best Si FET by 1.5-2x and 2-3.5x, respectively. Projected into the 10nm gate length regime, III-V on-Insulator, CNFET, and TFET are 1.25x, 2-3x, and 5-10x (for FO1 delays of 0.3ns, 0.1ns, and 1ns respectively) better than the ITRS target at the same gate length.
    Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2011
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    ABSTRACT: Summary form only given. Miniaturization of device feature size has improved both device density and device performance in the conventional scaling era. However, degradation of electrostatic gate control, increasing contribution of parasitics, and increasing power consumption have limited scalability. The slow-down of L<sub>g</sub> scaling has been compensated for by technology features such as strain engineering, high-κ dielectric, and novel channel materials and device structures. Looking forward, new trends for device design are expected. Particularly, considerable amount of attention is needed in 1) parasitics, and 2) understanding device design and its impact on the circuit-level environment. For advanced technologies and emerging devices, technology development and device design has to be revisited, as conventional methods of performance benchmarking are unable to capture the system-level power-constrained circuit design tradeoffs. In this paper, several issues on technology development are further addressed based on the study of device and circuit interactive design and optimization.
    Electron Devices Meeting (IEDM), 2010 IEEE International; 01/2011
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    ABSTRACT: Meeting reliability requirements is an increasingly more difficult challenge with each generation of CMOS technology. The disconnection between conventional one-size-fits-all reliability specifications and the wide range of circuit applications might be a huge waste of resources. By taking into consideration circuit- level figures of merit, a novel methodology to establish device reliability criteria that reflects real-world operation of devices in circuits is proposed and demonstrated. This "circuit-aware" methodology makes a real step toward realizing the goal of application-aware reliability standards which do not require additional measurements. The beauty is its simplicity - a simple transformation to solve an important problem. The simplicity makes it attractive as a standard methodology. I. INTRODUCTION A critical aspect of qualifying VLSI technology for full scale production is satisfying reliability criteria. As CMOS technology continues to advance, it is becoming increasingly more difficult for a new technology to meet all of its reliability specifications. Additionally, many of the reliability qualification specifications are based on seemingly arbitrary device parametric shifts and do not necessarily correlate with real world circuit behavior; product reliability in the field often shows no correlation with the qualification criteria. The current standard of a single device-level reliability specification, which is used to qualify all circuit applications for a particular technology, is illogical, wasteful, and painful. It makes little sense to universally trade performance for reliability or vice-versa regardless of the circuit application. Thus, there is a real and urgent need to develop reliability criteria that can reflect a particular circuit's actual application
    Proceedings of the 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, Sept. 12-16, 2011; 01/2011
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    ABSTRACT: By surmounting various obstacles across the spectrum from material synthesis to device fabrication and circuit considerations, we provide a solid foundation so that carbon-based technology can move forward towards the vision of engineering VLSI circuits, but further research is still needed to realize the material potential such as higher density CNT synthesis, better metal to CNT/graphene contacts, and air-stable doping of CNT.
    International Symposium on VLSI Technology, Systems, and Applications, Proceedings 01/2011;
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    ABSTRACT: Carbon Nanotube Field-Effect Transistors (CNFETs) are excellent candidates for designing highly energy-efficient future digital systems. However, carbon nanotubes (CNTs) are inherently highly subject to imperfections that pose major obstacles to robust CNFET digital VLSI. This paper summarizes commonly raised questions and concerns about CNFET technology through a series of frequently asked questions. The specific questions addressed in this paper are motivated by recent advances in the field since the publication of our earlier paper on frequently asked questions in the Proceedings of the 2009 Design Automation Conference.
    2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, November 7-10, 2011; 01/2011
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    ABSTRACT: Because of high carrier velocities and quasi-ballistic transport properties, carbon-based (nanotube, graphene) field effect transistors (CNFETs) are considered to be potential candidates to replace CMOS in future technology generations . Most prior modeling of CNFETs has involved complex models, such as NEGF , but to properly evaluate these devices in circuits and systems, efficient compact models are required. In this paper, a fully analytical model based on ballistic transport and careful analysis of quantum capacitances is developed. This model requires neither iteration nor numeric integration. The model agrees well with numerical simulation and, in the limit of good contacts, predicts that a new effect, source exhaustion (using up all available carriers in the source), should limit the current. The model has also been integrated into a system level design optimization program which evaluates optimal device parameters based on system-level design objectives. The CNFET is projected to achieve 5× chip-level speed up over PDSOI at 11 nm technology node for a high-performance four-core processor with 1.5M logic gates.
    Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
  • Source
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    ABSTRACT: We review recent efforts to capture the device nonidealities for circuit-level technology projection for Si CMOS. We also give some examples of simple compact model development for assessing the circuit-level performance of exploratory devices such as III-V FET, carbon nanotube transistor, and nanoelectromechanical (NEM) transistors and relays.
    Simulation of Semiconductor Processes and Devices, 2009. SISPAD '09. International Conference on; 10/2009
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    ABSTRACT: In this paper, we revisit the Si CMOS roadmap projection by taking into consideration the parasitic capacitances, which significantly affect the device performance beyond 32 nm technology. Capacitance components are analytically modeled and different design rules are examined.
    VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on; 05/2009
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    ABSTRACT: We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-kappa/metal gate) reach their limits and physical gate length can no longer be effectively scaled down. By judiciously engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of selective device structure scaling that will enable technology scaling and contacted gate pitch scaling for several generations beyond the currently perceived limits.
    IEEE Transactions on Electron Devices 03/2009; · 2.06 Impact Factor
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    ABSTRACT: Devices based on nanotubes and nanowires have been a popular research topic in the recent years. Many groups have shown promising experimental results in this area. In this paper, we examine the expected performances of 1-D and 2-D MOSFETs by numerical simulation and analytical models. We show that 1-D devices are not necessarily better than 2-D devices for future technologies, especially for low-channel densities and narrow gate widths, due to the parasitic capacitances and screening of the adjacent channels. For example, the delay improvement is overestimated from the intrinsic cases by at least 30%-60% from ignoring parasitics and channel screening effects, for W<sub>gate</sub><10 L<sub>g</sub> and channel densities from 400 to 25 mum. We propose a methodology for 1-D device design optimization, and a possible scaling path of 1-D devices down to 11 nm node. The analytical model is a first step toward a compact model for 1-D FETs.
    IEEE Transactions on Nanotechnology 12/2008; · 1.80 Impact Factor
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    ABSTRACT: We explore options for device scaling beyond the conventional scaling path. We examine the role of the parasitic capacitance for determining the performance of future one-dimensional FETs. We also explore a possible device scaling path that focuses on aggressive scaling of the contacted gate pitch, which provides performance improvements at both the device and circuit level.
    Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on; 11/2008
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    ABSTRACT: A simple and efficient model of carbon nanotube field effect transistor (CNFET) is necessary to perform system-level optimization. In this paper, an analytical model with no iteration or integration is developed, including an analytical electrostatic model for the surface potential and simplification of scattering effects. The model is computationally efficient, but includes essential physics such as DIBL effect and scattering.
    Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European; 10/2008
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    ABSTRACT: We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-k/metal gate) reach their limits. By carefully engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of device footprint and device structure scaling that will enable technology scaling for several generations beyond the currently perceived limits.
    VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on; 05/2008
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    ABSTRACT: This paper studies the parasitic capacitance of 1-dimensional (1D) and 2-dimensional (2D) MOSFETs by numerical simulation and analytical models. We show that 1D devices are not necessarily the better choice over 2D devices for future technologies, especially for low channel densities and narrow gate widths. For W<sub>gate</sub><10L<sub>g</sub>, the delay improvement is overestimated from the intrinsic case by at least 30%-60% from ignoring parasitics and channel screening effects, for channel density from 400/mum-25/mum. A methodology for 1D device design optimization is proposed, followed by a possible scaling path of 1D devices down to 11 nm node. The analytical model is a first step toward a compact model for 1D FETs.
    Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008