[show abstract][hide abstract] ABSTRACT: The precipitation of P in the emitter region of H3PO4 spray doped silicon for solar cell applications has been investigated by electron microscopy, X-ray microanalysis and electrical measurements after annealing for two different times. P, Si and O concentration profiles show that the composition of the phosphorous silicate glass (PSG) is in agreement with a solid solution of P2O5 in SiO2 and that P concentration is peaked at the PSG/Si interface. TEM observations have shown for the shorter annealing the formation of a 20 nm thick defect layer at the silicon surface; this layer evolves into a network of large rod-like monoclinic (or orthorhombic) SiP precipitates, which extend in depth up to about 100 nm for the longer treatment. The SiP crystal structure and the habit planes are the same as previously reported in literature. No deeper defect that could interact with the junction located at about 300 nm has been detected. Although the SiP precipitation takes place entirely at the Si surface, it is not significantly affected by the orientation of the crystals and by the texturing process. The amounts of both electrically active and inactive P obtained by the H3PO4 spray technique have been compared with the ones obtained by the conventional POCl3 technique. The former process presents a larger amount of inactive dopant, a finding that is in keeping with the microstructural and microanalytical observations. Instead the amount of active P is similar in the two cases, a result attributed to the precipitation and clustering phenomena of the excess dopant.
Solar Energy Materials and Solar Cells 11/2011; 95(11):3099–3105. · 4.63 Impact Factor
[show abstract][hide abstract] ABSTRACT: A process is developed for the fabrication of vertically arranged poly-silicon nanowires via a rigorously top-down batch process. The technique allows the production of wire arrays with larger linear density (projected on the surface) than those achievable with any of the other proposed top-down processes.
[show abstract][hide abstract] ABSTRACT: As far as the fabrication of ultradense crossbars is related to correspondingly dense wire arrays, the crossbar route to tera-scale integration depends on the availability of preparation techniques for wire arrays with density of 10(6) cm(-1) or more. For a planar arrangement this density implies a pitch of 10 nm or less, beyond the current possibility and close to the theoretical limit, assuming for the cross-point a minimum area of 10 nm(2). Further increase of density can only be achieved organizing the nanowires in a three-dimensional fashion. This paper describes a planar top-down process for the preparation of vertically arranged poly-silicon nanowires. The technique is expected to allow the production of wire arrays with linear density (projected on the surface) larger than those achievable with any other proposed top-down processes. Used for the fabrication of the bottom wire array of crossbars, this process should allow an eventual cross-point density of the order of 10(12) cm(-2), thus being a candidate technology for tera-scale integration.
Semiconductor Science and Technology 01/2011; 26(4):045005. · 1.92 Impact Factor
[show abstract][hide abstract] ABSTRACT: The observation that the thermal conductivity of single-crystalline silicon nanowires with diameter on the length scale of 25 nm is lower than that of bulk material by two orders of magnitude has attracted the interest onto silicon as a potentially effective thermoelectric material. However, the potential interest has a hope of transforming in a practical interest only if poly-crystalline silicon can replace single crystalline silicon and the preparation of nanowires does not involve any advanced photolithography. In this work we show that a technique, based on the controlled etching and ?lling of recessed regions and employing standard photolithography and deposition-etching methods, succeeds in the preparation of poly-crystalline silicon nanowires (with diameter of 25 nm and length on the centimetre scale) at a linear density of 3E6 cm^-1.
[show abstract][hide abstract] ABSTRACT: The race of integrated-circuit technology towards high bit density has already brought transistor densities of the order of 10(9) cm(-2), while keeping conventional circuit layouts. Crossbar structures are widely believed to meet the requirements of high bit density along with sustainable interconnection complexity avoiding the dramatic cost increase of the manufacturing facilities required by advanced lithography. In this work we demonstrate the possibility of producing poly-Si nanowires preserving bulk electrical properties that are nonetheless so dense as to allow cross-point density in excess of 10(11) cm(-2). This result could be achieved by organizing silicon nanowires in nearly vertical arrays.
Semiconductor Science and Technology 08/2010; 25(9):095011. · 1.92 Impact Factor
[show abstract][hide abstract] ABSTRACT: Electron states at the SiO <sub>2</sub>/4 H – SiC interface have been investigated using capacitor structures and especially, the influence of excess nitrogen, introduced by ion implantation, at the interface is studied in detail. Implanted and nonimplanted n-type samples with an interfacial concentration of nitrogen of ∼10<sup>19</sup> cm <sup>-3</sup> and 10<sup>16</sup> cm <sup>-3</sup> , respectively, were analyzed by capacitance-voltage (C-V) measurements, performed at different temperatures and probe frequencies, and thermal dielectric relaxation current (TDRC) measurements performed in the temperature range of 35–295 K. Three main categories of electron states are disclosed, true interface states (D<sub>it</sub>) , fast near interface states ( NIT <sub> ox </sub><sup> fast </sup>) and slow near interface states ( NIT <sub> ox </sub><sup> slow </sup>) . The density versus energy distributions of D<sub>it</sub> and NIT <sub> ox </sub><sup> fast </sup> have been deduced from the TDRC data and they are shown to give a close quantitative agreement with the shape and frequency dependence of the C-V curves. Further, the amount of NIT <sub> ox </sub><sup> slow </sup> extracted from TDRC is demonstrated to be responsible for the parallel shifts and hysterezis effects occurring in the C-V characteristics. All three categories of electron states are reduced in concentration in the implanted samples. This holds particularly for NIT <sub> ox </sub><sup><-
roman>fast </sup> with a peak at ∼0.1 eV below the conduction band edge of 4H–SiC that is suppressed by at least two orders of magnitude relative to the nonimplanted samples. The decrease for D<sub>it</sub> is also substantial (a factor of ∼10 ) while the loss for NIT <sub> ox </sub><sup> slow </sup> is considerably smaller (only ∼30 % ). The results provide firm evidence that NIT <sub> ox </sub><sup> fast </sup> and NIT <sub> ox </sub><sup> slow </sup> do not originate from the same kind of defect center.
Journal of Applied Physics 08/2010; · 2.21 Impact Factor
[show abstract][hide abstract] ABSTRACT: The electrical characteristics of n -metal oxide semiconductor field effect transistors ( n -MOSFETs) fabricated on 4H -SiC with a process based on nitrogen (N) implantation in the channel region before the growth of the gate oxide are reported as a function of the N concentration at the SiO <sub>2</sub>/ SiC interface. A strong correlation among the increase in the N concentration, the reduction of the interface state density near the conduction band and the improvement of the MOSFET performance was obtained. Hall-effect measurements were used to determine the electron mobility and the free carrier concentration in the MOSFET channel. Among the investigated combinations of N dose and oxidation time, the one with the higher dose and the shorter time produces MOSFETs with the higher N concentration at the SiO <sub>2</sub>/ SiC interface and the best electrical characteristics. This superior performance is obtained in spite of the lowering of the bulk mobility in the channel of this sample, a negative effect probably ascribable to the incomplete recovery of the implantation damage or to the high density of interstitial nitrogen atoms present in the channel region. However, evidence of extended defects, clusters or nanoparticles was not observed by transmission electron microscopy analyses in any of the investigated SiC MOSFET devices.
Journal of Applied Physics 03/2010; · 2.21 Impact Factor
[show abstract][hide abstract] ABSTRACT: In this paper the electrical and structural characteristics of n-MOSFETs fabricated on 4H-SiC with a process based on nitrogen (N) implantation in the channel region before the growth of the gate oxide are reported for low (5x10 18 cm -3) and high (6x10 19 cm -3) N concentration at the SiO 2 /SiC interface. The electron mobility and the free carrier concentration in the MOSFET channel were evaluated by Hall effect measurement. The MOSFETs with the higher N concentration had the best electrical characteristics in terms of threshold voltage and field effect mobility, in spite of a lowering of the electron mobility in the channel. The latter is a negative drawback of the fabrication process that probably can be ascribed to an incomplete recovery of the implantation damage or to a high density of interstitial N atoms present in the channel region. In fact, the MOSFETs with the superior electrical performances were fabricated with the higher N + dose and the shorter thermal oxidation time. However, no evidence of extended defects, clusters or nano-particles in SiC at the interface with the gate oxide was found in every SiC MOSFETs devices observed by electron transmission microscopy .
[show abstract][hide abstract] ABSTRACT: This study compares p-MOS capacitors fabricated on N+ implanted and on virgin 4H-SiC. The former sample have N at the SiO2/SiC interface, the latter have not. To investigate the presence of deep and shallow hole traps at the SiO2/SiC interface, high frequency and quasi-static capacitance voltage measurements under dark have been compared for bias sweeping from accumulation to depletion and from depletion to accumulation, the latter after white light illumination. The presence of N has an effect on the density of the shallow donor like traps but none effect on the deep ones. The positive charge trapped in the oxide and/or at the oxide interface after equivalent tunneling hole injection have been compared and are equivalent. Time dependent dielectric breakdown tests have been compared too. The oxide grown on N+implanted SiC broken at lower electric field.
[show abstract][hide abstract] ABSTRACT: A gate oxide obtained by wet oxidation of SiC preimplanted with nitrogen has been investigated on MOS capacitors and implemented in a n-channel MOSFET technology. Different implantation fluences and energies in the ranges 1.5 X 10<sup>13</sup>-1 X 10<sup>15</sup> cm <sup>-2</sup> and 2.5-10 keV, respectively, were used with the aims to study the effect of the nitrogen concentration at the SiO<sub>2</sub>/SiC interface on MOSFET performance. The highest dose, which is able to amorphize a surface SiC layer, was also employed to take advantage of the faster oxidation rate of amorphous phase with respect to crystalline one. The electron interface trap density near the conduction band has been evaluated with different techniques both on MOS capacitors and MOSFET devices; a good agreement among the measured values has been attained. A strong reduction of the electron interface traps density located near the conduction band has been obtained in the samples with a high nitrogen concentration at the SiO<sub>2</sub>/SiC interface. The MOSFETs with the highest nitrogen concentration at the interface (~1 X 10<sup>19</sup> cm <sup>-3</sup>) present the highest channel mobility (21.9 cm<sup>2</sup>/V .s), the lowest threshold voltage (2.4 V), and the smallest subthreshold swing (310 mV/decade at drain current of 10 <sup>-11</sup> A).
IEEE Transactions on Electron Devices 09/2008; · 2.06 Impact Factor
[show abstract][hide abstract] ABSTRACT: Normally off 4H-SiC MOSFET devices have been fabricated on a p-type semiconductor and electrically characterized at different temperatures. A gate oxide obtained by nitrogen ion implantation performed before the thermal oxidation of SiC has been implemented in n-channel MOSFET technology. Two samples with a nitrogen concentration at the SiO<sub>2</sub>/SiC interface of 5 X 10<sup>18</sup> and 1.5 X 10<sup>19</sup> cm<sup>-3</sup> and one unimplanted sample have been manufactured. The sample with the highest N concentration at the interface presents the highest channel mobility and the lowest threshold voltage. For increasing temperature, in all the samples, the threshold voltage decreases, and the electron channel mobility increases. The latter case attains a maximum value of about 40 cm<sup>2</sup>/V ldr s at 200degC for the sample with the highest N concentration. These trends are explained by the reduction of interface electron traps in the upper half of the band gap toward the conduction band edge. These results demonstrate that N implantation can be effectively used to improve the electrical performances of an n-type surface channel 4H-SiC MOSFET.
IEEE Transactions on Electron Devices 05/2008; · 2.06 Impact Factor
[show abstract][hide abstract] ABSTRACT: In this letter, it is shown how the application of a Z-contrast scanning transmission electron microscopy technique to the study of the dopant signal in ultrashallow junctions in Si can lead, in the case of As in Si, to a quantitative determination of the dopant depth profile at subnanometer resolution. The quantitative results thus obtained demonstrate that As accumulates on the Si side of the SiO2 / Si interface with a negligible loss of dopant into the oxide. Modeling of the effect indicates that segregation occurring during the recrystallization of the implanted layer is the dominant cause of this dopant pileup.
[show abstract][hide abstract] ABSTRACT: The redistribution during annealing of low-energy B implants in SOI structures and in bulk Si have been investigated by comparing Secondary Ion Mass Spectrometry (SIMS) and simulated profiles. Samples preamorphised with Ge at different implantation energies have been prepared in order to investigate the effects of the damage position on B diffusion. The specimens have been subsequently B implanted at 500 eV with doses 2times10<sup>13</sup> and 2times10<sup>14</sup> cm<sup>-2</sup> and annealed between 700 and 1100degC. SIMS profiles show a B pile-up in the first few nanometres of the Si matrix on the Si surface. Simulations of diffused profiles indicate that the B redistribution upon annealing can be explained by assuming that the mobility of the dopant which arrives in proximity of the surface is practically annulled. The amount of B trapped at the surface is maximum at the temperatures around 800degC, when more than 80% of the implanted dopant is made immobile and electrically inactive. The trapped B increases with reducing the depth of the amorphous layer and it is higher in the bulk Si than in SOI. By comparing Hall measurements and the amount of B not trapped at the surface, we also estimate the amount of B that aggregates inside the Si lattice in form of clusters (BICs). For the B dose of 2times10<sup>14</sup> cm<sup>-3</sup>, after isochronal annealing of 60 s, the amount of BICs is about 3-4times10<sup>13</sup> cm<sup>-2</sup> at the lowest temperatures and tends to vanish at high temperatures.
Advanced Thermal Processing of Semiconductors, 2007. RTP 2007. 15th International Conference on; 11/2007
[show abstract][hide abstract] ABSTRACT: Aiming to minimize the interface state density, we fabricated MOS capacitors on n-type 4H-SiC by using wet oxidation of nitrogen implanted layers. We investigated a wide range of implantation dose, including a high dose able to amorphise a surface SiC layer with the intent to reduce the oxidation time. The oxide quality and the SiO 2 -SiC interface properties were characterized by capacitance-voltage measurements of the MOS capacitors. The proposed process, in which nitrogen is ion-implanted on SiC layer before a wet oxidation, is effective to reduce the density of interface states near the conduction band edge if a high concentration of nitrogen is introduced at the SiO 2 -SiC interface. We found that only the nitrogen implanted at the oxide-SiC interface reduces the interface states and we did not observe the generation of fixed positive charges in the oxide as a consequence of nitrogen implantation. Furthermore, the concentration of the slow traps evaluated from the Slow Trap Profiling technique was low and did not depend on the nitrogen implantation fluence.
[show abstract][hide abstract] ABSTRACT: The manufacture process and the electrical characterization of MOS devices fabricated by wet oxidation of N+ implanted n-type 4H–SiC are here presented. Different implantation fluence and energy values were used with the aims to study the effect of the N concentration both at the SiO2/SiC interface and within the SiO2 film. High doses, able to amorphise a surface SiC layer to take advantage of the faster oxidation rate of amorphous with respect to crystalline SiC, were also evaluated. The electrical quality of the SiO2/SiC system was characterized by capacitance–voltage measurements of MOS capacitors. The analyses of the collected data show that only the implanted N which is located at the oxide–SiC interfaces is effective to reduce the interface states density. On the contrary, the interface states density remains high (the same of an un-implanted reference sample) when the implanted N is completely embedded in the region consumed by the oxidation. Furthermore, none generation of fixed positive charges in the oxide was found as a consequence of the different N concentrations enclosed in the oxide films. These results were independent of the amorphisation of the implanted layer by the N+ ions. Our results demonstrate that by using a suitable N ion implantation and an appropriate wet oxidation treatment, it is possible to obtain a reduced thermal budget process able to decrease the interface state density near the conduction band edge. The proposed approach should be interesting for the development of the MOSFET technology on SiC.