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IEEE Trans. VLSI Syst. 01/2012; 20:211-224.
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ACM Trans. Design Autom. Electr. Syst. 01/2010; 15.
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Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010; 01/2010
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Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009; 01/2009
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IEEE Trans. VLSI Syst. 01/2009; 17:1495-1507.
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IEICE Transactions. 01/2009; 92-A:3061-3069.
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Integration. 01/2009; 42:193-202.
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ABSTRACT: In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model order reduction techniques to reduce the circuit matrices before the simulation. Different from the (miproved) extended Krylov subspace methods EKS/IEKS [15, 2], ETBR performs fast truncated balanced realization on response Grammian to reduce the original system with the similar computation costs of EKS. ETBR also avoids the adverse explicit moment representation of the input signals. Instead, it uses spectrum representation of input signals by fast Fourier transformation. As a result, ETBR is more flexible for different types of input sources and can better capture the high frequency contents than EKS, and this leads to more accurate results especially for fast changing input signals. Experimental results on a number of large networks (up to one million nodes) show that, given the same order of the reduced model, ETBR is indeed more accurate than the EKS method especially for input sources rich in high-frequency components. ETBR also shows similar computation costs of EKS and less memory consumption than EKS.
Design, Automation and Test in Europe, 2008. DATE '08; 04/2008
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2008 International Conference on Computer-Aided Design (ICCAD'08), November 10-13, 2008, San Jose, CA, USA; 01/2008
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Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008; 01/2008
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Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008; 01/2008
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ABSTRACT: In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and the Krylov subspace projection-based model order reduction methods. The new approach, called hiePrimor, first partitions a large interconnect circuit into a number of smaller subcircuits and then performs the projection-based model order reduction on each of subcircuits in isolation and on the top-level circuit thereafter. The new approach is very amenable for exploiting the multi-core based parallel computing platforms to significantly speed up the reduction process. Theoretically we show that hiePrimor can deliver the same accuracy as the flat reduction method given the same reduction order and it can also preserve the passivity of the reduced models as well. We also show that partitioning has large impacts on the performance of hierarchical reduction and the minimum-span objective should be required to attain the best performance for hierarchical reduction. The proposed method is suitable for reducing large global interconnects like coupled bus, transmission lines, large clock nets in the post-layout stage. Experimental results demonstrate that hiePrimor can be significantly faster and more scalable than the flat projection methods like PRIMA and be order of magnitude faster than PRIMA with parallel computing without loss of accuracy. Interconnect circuits with up to 4 million nodes can be analyzed in a few minutes even in Matlab by the new method.
Integration, the VLSI Journal.
