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ABSTRACT: This paper presents a multi-loop voltage-controlled buck converter that operates at a wide range of programmable switching frequency and works over an input voltage range of 3.5 V to 60 V and load current up to 3 A. The output voltage can be externally set between 0.9 V and 20 V. A major challenge was incorporating line feed-forward technique while having a programmable switching frequency between 200 KHz and 2 MHz. A design technique to implement this feature, low-power mode detection using zero-cross detector, and multi-loop control to improve transient response will be presented. The converter fabricated in 0.5 mum process consumes 60 muA in low-power mode.
Energy Conversion Congress and Exposition, 2009. ECCE 2009. IEEE; 10/2009
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ABSTRACT: This paper presents a precision current sensor featuring a high voltage, high gain (~ 140 dB), and low input offset ( < 1 mV) current sense amplifier. This amplifier does not require offset trimming even for low offset applications. It is a single stage amplifier that has a common gate pMOS differential input pair, which makes it inherently stable. This amplifier topology allows for a wide input common-mode range, thus increasing the versatility of current sensing circuit.
Circuits and Systems I: Regular Papers, IEEE Transactions on 07/2008; · 1.97 Impact Factor
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ABSTRACT: An implementation of a compact and programmable 10-bits floating-gate digital-to-analog converter (FGDAC) is described. In this implementation, nonvolatile floating-gate voltage references (epots) are employed together with unity-size capacitors to obtain the binary-weighted scale factors. The FGDAC, fabricated in a 0.5- mum CMOS process, occupies 0.208 mm<sup>2</sup> of die area. The stored epot voltages drift 10_3% over the period of ten years at 25 degC and exhibit temperature coefficients of less than 37 ppm/degC. With the proposed design, INL and DNL values less than plusmn0.5LSB (LSB = 3 mV) and SFDR around 63 dB are obtained.
Circuits and Systems I: Regular Papers, IEEE Transactions on 06/2008; · 1.97 Impact Factor
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ABSTRACT: In this paper, an implementation of a tunable highly linear floating resistor that can be fully integrated in CMOS technology is presented. The second-order effects of a single MOS transistor operating in the triode operation regime are described, and a common-mode linearization technique is applied to suppress these nonlinearities. This technique is implemented by utilizing a low-power circuit design strategy that exploits the capacitive coupling and the charge storage properties of floating-gate transistors. The resistance of the proposed circuit is tuned by utilizing the Fowler-Nordheim tunneling and hot-electron injection quantum-mechanical phenomena. We demonstrate the use of this resistor in highly linear amplifier. We present experimental data from the chips that were fabricated in a 0.5- CMOS process. We show that this resistor exhibits 0.024% total harmonic distortion (THD) for a sine wave with amplitude. Also, we show the programmability of the amplifier gain using the proposed tunable resistor.
Circuits and Systems I: Regular Papers, IEEE Transactions on 06/2008; · 1.97 Impact Factor
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ABSTRACT: A reconfigurable implementation of distributed arithmetic (DA) for post-processing applications is described. The input of DA is received in digital form and its analog coefficients are set by using the floating-gate voltage references. The effect of the offset and gain errors on DA computational accuracy is analyzed, and theoretical results for the limitations of this design strategy are presented. This architecture is fabricated in a 0.5-mum CMOS process, and configured as a 16-tap finite impulse response (FIR) filter to demonstrate the reconfigurability and computational efficiency. The measurement results for comb, low-pass, and bandpass filters at 32/50-kHz sampling frequencies are presented. This implementation occupies around 1.125 mm<sup>2</sup> of die area and consumes 16 mW of static power. The filter order can be increased at the cost of 0.011 mm<sup>2</sup> of die area and 0.02 mW of power per tap.
Circuits and Systems I: Regular Papers, IEEE Transactions on 04/2008; · 1.97 Impact Factor
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ABSTRACT: We present an implementation of a reconfigurable 16-tap finite impulse response filter for post-processing applications. This filter exploits the distributed arithmetic technique for signal processing and floating-gate voltage references for setting tunable analog coefficients. The filter is fabricated in 0.5mum CMOS process, and its order can be increased at the cost of 0.011mm<sup>2</sup> of die area and 0.02mW of power per tap. Measurement results for low-pass and band-pass filters at 50kHz sampling frequency are presented.
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007
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ABSTRACT: We present an implementation of a 4-bit binary-weighted-resistor DAC to be used in quantizers. It is built by using tunable floating-gate CMOS resistors, which exploit the capacitive coupling and voltage storage capabilities of floating-gate transistors and employ scaled-gate linearization technique to suppress the MOSFET nonlinearities. The resistance of these resistors drifts 1.6 middot 10<sup>-3</sup>% over the period of 10 years at 25degC. By using these resistors, 15-bit accurate DAC is implemented in 0.5mum CMOS process
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE; 10/2006
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ABSTRACT: We present a novel analog VLSI implementation of visual motion computation based on the lateral inhibition and positive feedback mechanisms that are inherent in the hysteretic winner-take-all circuit. By use of an input-dependent bias current and threshold mechanism, the circuit resets itself to prepare for another motion computation. This implementation was inspired by the Barlow-Levick model of direction selectivity in the rabbit retina. Each pixel uses 33 transistors and two small capacitors to detect the direction of motion and can be altered with the addition of six more transistors to measure the interpixel transit time. Simulation results and measurements from fabricated VLSI designs are presented to show the operation of the circuits
Circuits and Systems II: Express Briefs, IEEE Transactions on 09/2006; · 1.41 Impact Factor
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ABSTRACT: This paper describes an implementation of a low-voltage CMOS buffer employing a negative feedback to improve its performance. Floating-gate transistors are incorporated to obtain low-threshold transistors and to increase the input/output voltage swing of the circuit operating at 1.2V. The designed circuit is fabricated in 0.5mum CMOS process, and occupies 0.0214mm<sup>2</sup>. It achieves total harmonic distortion (THD) of 48dB for 10kHz 0.6V<sub>pp</sub> sinusoidal input signal
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on; 06/2006
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ABSTRACT: This paper describes an implementation of a tunable CMOS resistor that can be fully integrated in a standard CMOS technology with low-power and low-voltage applications. It is built by exploiting the capacitive coupling and voltage storage capabilities of a floating-gate transistor. Also, a scaled-gate linearization technique is utilized to suppress the transistor nonlinearities in the triode region. The resistance of the proposed circuit is tuned by utilizing Fowler-Nordheim tunnelling and hot-electron injection quantum mechanical phenomena. We present experimental data from the chip that was fabricated in 0.5mum CMOS process, and show that this resistor exhibits total harmonic distortion (THD) better than 7-bit linearity for 1KHz 1V<sub>pp</sub> sinusoidal input
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on; 06/2006
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ABSTRACT: We present implementations of highly linear amplifier and multiplier circuits that employ a linear CMOS resistor. This tunable resistor is built by utilizing the common-mode linearization technique, and by exploiting the gate-coupling and charge-storage characteristics of the floating-gate transistors. It exhibits 0.01% THD for 1V<sub>pp </sub> input. Also, the amplifier has an input linear range of 2.5V<sub>pp</sub> for differential and single-ended inputs, and achieves 0.018% THD for 1V<sub>pp</sub> differential input
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005; 10/2005
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ABSTRACT: In this paper, we propose implementations of highly linear floating-gate CMOS resistors that can be fully integrated in CMOS technology. Also, we analyze the second order effects of a single transistor operating in the linear operation regime and apply a linearization technique to suppress these nonlinearities. The resistance of the proposed circuits can be tuned by utilizing Fowler-Nordheim tunnelling and hot-electron injection quantum mechanical phenomena. Finally, we present experimental data from the chips that were fabricated in 0.5 μm CMOS process.
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; 06/2005
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ABSTRACT: This paper describes an implementation of a compact and low-power 10-bit floating-gate digital-to-analog converter (FGDAC). Nonvolatile floating-gate voltage references are utilized to build a charge amplifier DAC architecture. This novel implementation eliminates the large element spread and resolution trade-off in the traditional design of a charge amplifier voltage-output DAC. The FGDAC was fabricated in a 0.5 micrometre CMOS process and its total area is 0.0522 mm<sup>2</sup>. The presented experimental data shows that INL and DNL values less than plus or minus 0.5 LSB (0.68 mV) are easily achievable. This structure enables digital to analog conversion with programmable linearly or nonlinearly spaced levels.
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; 06/2005
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ABSTRACT: Visual motion information provides a variety of clues that enable biological organisms from insects to primates to efficiently navigate in unstructured environments. We present modular mixed-signal very large-scale integration (VLSI) implementations of the three most prominent biological models of visual motion detection. A novel feature of these designs is the use of spike integration circuitry to implement the necessary temporal filtering. We show how such modular VLSI building blocks make it possible to build highly powerful and flexible vision systems. These three biomimetic motion algorithms are fully characterized and compared in performance. The visual motion detection models are each implemented on separate VLSI chips, but utilize a common silicon retina chip to transmit changes in contrast, and thus four separate mixed-signal VLSI designs are described. Characterization results of these sensors show that each has a saturating response to contrast to moving stimuli, and that the direction of motion of a sinusoidal grating can be detected down to less than 5% contrast, and over more than an order of magnitude in velocity, while retaining modest power consumption.
Circuits and Systems I: Regular Papers, IEEE Transactions on 02/2005; · 1.97 Impact Factor
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ABSTRACT: In this paper, we describe implementations of binary-weighted and equal capacitance floating gate digital-analog converters (FGDACs). We improve the accuracy of charge amplifier DAC circuits and reduce their large element spread by utilizing epots in their implementations. We analyze these circuits and present experimental data from the chips that were fabricated in 0.5μm CMOS process available through MOSIS. The characterization results prove that by using the equal capacitance FGDAC structure, we can obtain very accurate results while eliminating the problems caused by the large element spread.
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on; 06/2004
