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ABSTRACT: One of the major problems of p-i-n tunneling field-effect transistor (TFET) is the reliability due to the strong electric field near the tunneling junction. In this paper, using technology computer-aided design simulation, we show that the insertion of a thin n-layer into the tunneling junction of the p-i-n TFET (p-n-i-n TFET) not only enhances its drive current, as has been previously reported, but also improves its reliability. As compared with the conventional p-i-n TFET, we demonstrate the following properties of the p-n-i-n TFET: 1) The normal component of the electric field near the tunneling junction is reduced, and therefore, the field-driven interface-trap generation can be reduced. This can be further reduced by properly aligning the gate electrode with respect to the tunneling junction. 2) The threshold-voltage shift due to the dielectric charge generated near the tunneling junction is significantly reduced. 3) The variation of the threshold voltage to the oxide and bulk thickness variations is also reduced.
IEEE Transactions on Electron Devices 08/2011; · 2.32 Impact Factor
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ABSTRACT: A novel recovery-free interface-trap measurement method is presented in detail. This method is the modification of the conventional charge pumping (CP) by extending the pulse low level to the stress-bias and minimizing the pulse high-level duty cycle to suppress the recovery effect. The method is applied to study the negative-bias temperature instability in p-MOSFETs. As compared with the conventional CP, a much larger interface-trap generation under stress is observed by the new method. A power law time dependence ( ~ t <sup>n</sup>) of interface-trap generation is observed. The index n is less than that derived from conventional CP and increases with temperature, demonstrating a dispersive process involved in the trap generation dynamics.
IEEE Transactions on Electron Devices 03/2009; · 2.32 Impact Factor
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ABSTRACT: In this work, we combine our recently developed recovery free on-the-fly interface traps measurement (OFIT) and fast-pulsed-measurement (FPM) to conduct a comprehensive study of BTI degradations for both n- and p-MOSFETs with SiON gate dielectric. The results provide the most reliable data for the understanding and modeling of BTI degradation and also provide new insights to re-access the impact of BTI in logic and analog circuits and SRAM applications.
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International; 06/2008
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ABSTRACT: Our recent investigations and understanding of the negative bias temperature instability (NBTI) degradation in p-MOSFETs with ultrathin SiON gate dielectric are reviewed. The progressive understanding of NBTI mechanism is mainly related to the novel measurement techniques we developed. We show in this paper the following: 1) For the conventional charge pumping and direct-current current-voltage interface trap measurement, the interface trap density N<sub>it</sub> is underestimated due to the recovery during measurement delay. The existing N<sub>it</sub> data should be reexamined; 2) an ultrafast pulsed I-V method [fast pulsed measurement (FPM)] is developed to measure DeltaV<sub>th</sub> with measurement time t<sub>M</sub> = 100 ns. It can be considered as free from recovery during measurement; 3) due to the degradation during the initial threshold voltage measurement, the existing slow on-the-fly (OTF) DeltaV<sub>th</sub> measurement distorts (overestimates) the slope and induces a kink at early stress time in the Log-Log curve of the time evolution of NBTI degradation. A fast OTF DeltaV<sub>th</sub> measurement method is developed to overcome this problem; 4) a novel OTF interface trap (OFIT) measurement method is developed which is free from interface trap recovery during measurement. The OFIT measurement provides the most reliable data to inspect the interface trap R-D model; 5) combining the OFIT and FPM measurements, we decompose the NBTI DeltaV<sub>th</sub> into two components: A slow DeltaV<sub>th</sub> <sup>it</sup> component contributed by with a slow recovery time longer than 50mus and a fast DeltaV<sub>th</sub> <sup>ox</sup> component contributed by DeltaV<sub>ox</sub> with a broad spectrum of recovery time, including a component with very fast recovery time (100 ns); and 6) the dynamic degradation by DeltaV<sub>th</sub> <sup>it</sup> component is frequency-independent and can be measured by a dc method, whereas the dynamic degradation DeltaV<sub>th</sub-
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> <sup>ox</sup> by component measured by FPM is increased by increasing frequency. The ten-year lifetime of the p-MOSFETs is mainly determined by the degradation of the DeltaV<sub>th</sub> <sup>it</sup> component.
IEEE Transactions on Device and Materials Reliability 04/2008; · 1.54 Impact Factor
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ABSTRACT: For the first time, we developed an on-the-fly method OFIT to measure the interface trap density N IT without recovery during measurement. The OFIT produces the most reliable experimental data of the interface trap generation dynamics under stress and therefore provides a solid ground to check various modeling work. The slope n of t n time evolution of ∆N IT under stress is temperature dependent, supporting dispersive Hydrogen transport in the oxide. Comparing OFIT data with the data measured by ultra-fast pulsed V th measurement, we successfully decompose the NBTI ∆V TH into interface trap component ∆V TH IT and oxide charge component ∆V TH OX quantitatively for the p-MOSFETs with SiON gate dielectric.
