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ABSTRACT: The very significant growth of the wireless communication industry has spawned tremendous interest in the development of high performances radio frequencies (RF) components. Micro Electro Mechanical Systems (MEMS) are good candidates to allow reconfigurable RF functions such as filters, oscillators or antennas. This paper will focus on the MEMS electromechanical resonators which show interesting performances to replace SAW filters or quartz reference oscillators, allowing smaller integrated functions with lower power consumption. The resonant frequency depends on the material properties, such as Young's modulus and density, and on the movable mechanical structure dimensions (beam length defined by photolithography). Thus, it is possible to obtain multi frequencies resonators on a wafer. The resonator performance (frequency, quality factor) strongly depends on the environment, like moisture or pressure, which imply the need for a vacuum package. This paper will present first resonator mechanisms and mechanical behaviors followed by state of the art descriptions with applications and specifications overview. Then MEMS resonator developments at STMicroelectronics including FEM analysis, technological developments and characterization are detailed.
03/2008;
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ABSTRACT: The optimization of the small and large signal performances of a radio frequency (RF)-LDMOS is presented via the achievement of a novel LDMOS architecture. Specific process steps are introduced into a 0.25-mum BiCMOS technology and precisely described to realize a fully salicided gate RF-LDMOS architecture. Significant improvement is obtained on the small-signal - f<sub>T</sub> and F<sub>max</sub> - and power performances while maintaining good dc characteristics
IEEE Transactions on Electron Devices 05/2007; · 2.32 Impact Factor
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ABSTRACT: This papers presents new results on silicon I-MOS devices, (where the source and the drain are doped of opposite type) obtained by an adaptation of a conventional CMOS process. Fabricated devices are fully functional down to 55nm of gate length, but the influence of the gate becomes strongly reduced for shorter devices due to technological limitations. Nevertheless, the smallest device, with a 17nm gate length and with an avalanche threshold of 5.3V, is reported. The corresponding output current-voltage features an equivalent resistance as low as 66 Omegamiddotmum. For all devices, the maximum current is only limited by the contacts destruction, positioning the measured value of 4700 muA/mum among the highest ever reported for a MOS device. In addition, it is shown that the extrapolated I<sub>on</sub>/I<sub>off </sub> figure of merit is close to complying with the specifications imposed to the HP flavor of the ITRS'05 roadmap
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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ABSTRACT: An asymmetrical spacer LDMOSFET integrated in a 0.25μm BiCMOS technology is presented. Improved RF performances are obtained with this new architecture: f<sub>T</sub> close to 35GHz with BVds larger than 15V. Process integration strategy is discussed. Impact on the other devices is described.
Bipolar/BiCMOS Circuits and Technology Meeting, 2006; 11/2006
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C. Gallon,
C. Fenouillet-Beranger,
A. Vandooren,
F. Boeuf,
S. Monfray,
F. Payet,
S. Orain,
V. Fiori,
F. Salvetti,
N. Loubet, [......],
D. Delille, F. Judong,
C. Perrot,
M. Hopstaken,
P. Scheblin,
P. Rivallin,
L. Brevard,
O. Faynot,
S. Cristoloveanu,
T. Skotnicki
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ABSTRACT: The fully depleted (FD) SOI MOSFET is generally considered as one of the best candidates for next CMOS technology nodes. However, new technological boosters need to be introduced in the classical FD SOI process flow to reach the very aggressive I<sub>on</sub>/I<sub>off</sub> specifications predicted by the ITRS roadmap. The use of a thin buried oxide (BOX) on FD SOI is still a controversial subject, despite recent publications that have demonstrated its interest for improvement of short channel effect (SCE) control, especially with a ground plane (GP) integration (Tsuchiya et al.). In order to improve the device performances, a strained "contact etch stop layer" (CESL) technique has been successfully demonstrated to induce strain into the channel of bulk devices (Thompson et al., 2002) as well as in ultra-thin FD SOI devices (Singh et al., 2005 and Gallon et al., 2006). However, its compatibility with the specific technological features of FD SOI devices, such as silicon film thickness (T<sub>S1</sub>) variations, BOX material and BOX thickness (T<sub>BOX</sub>), raised source/drain architecture, has yet to be clarified. In this paper, we demonstrate, by electrical and mechanical simulations, the interest of thin BOX with GP, combined with a strained liner. These simulations have then been validated by measurements, showing excellent I<sub>on</sub>/I<sub>off</sub> pMOS performances
International SOI Conference, 2006 IEEE; 11/2006
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ABSTRACT: LDMOSFET optimization for RF power applications is discussed. Starting from a quite standard transistor, a new architecture has been developed to reach high RF performances without sacrificing DC characteristics. The parasitic elements affecting the RF performances have been identified and reduced. The optimized device presents the following performances: BVds=15V, W.Ron lower than 3 Ohm.mm and f<sub>T</sub> larger than 30 GHz.
Bipolar/BiCMOS Circuits and Technology Meeting, 2005. Proceedings of the; 11/2005
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F. Arnaud,
B. Duriez,
B. Tavel,
L. Pain,
J. Todeschini,
M. Jurdit,
Y. Laplanche,
F. Boeuf,
F. Salvetti,
D. Lenoble, [......],
D. Roy,
M. Denais,
K. Rochereau,
R. Difrenza,
N. Planes,
H. Brut,
L. Vishnobulta,
D. Reber,
P. Stolk,
M. Woo
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ABSTRACT: A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 μm<sup>2</sup> 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully working 0.5 μm<sup>2</sup> bit-cells with 240mV of SNM and 35 μA of cell current at 1.2V operation were obtained. The GP transistor drive currents of 875 μA/ μm and 400 μA/ μm for NMOS and PMOS respectively are obtained at V<sub>dd</sub> = 1V, Ioff = 100nA/um. Using the same CMOS flow, 65nm analog transistor parameters are derived for the first time, showing Vt matching (Avt=2.2mV. μm) and analog voltage gain factor (G<sub>m</sub>/G<sub>d</sub>>2000 for L = 10 μm) at the leading edge for this process technology. NBTI criteria at 125°C for both LP and GP transistors are presented and characterized at overdrive conditions.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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L. Pain,
M. Charpin,
Y. Laplanche,
J. Todeschini,
H. Leininger,
S. Tourniol,
R. Faure,
X. Bossy,
R. Palla,
A. Beverina, [......],
Y. Le Friec,
F. Leverd,
V. De Jonghe,
E. Josse,
O. Hinsinger,
P. Brun,
D. Henry,
M Woo,
P. Stolk,
F. Arnaud
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ABSTRACT: In this paper, SRAM cell device manufacture using shaped electron beam lithography was developed. TEM view of SRAM cell was showed.
Microprocesses and Nanotechnology Conference, 2003. Digest of Papers. 2003 International; 11/2003
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M. Bopp,
P. Coronel, F. Judong,
K. Jouannic,
A. Talbot,
D. Ristoiu,
C. Pribat,
N. Bardos,
F. Pico,
M.P. Samson,
P. Dainesi,
A. M. Ionescu,
T. Skotnicki
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ABSTRACT: Annealing silicon at high temperatures in hydrogen ambiance has been reported to induce surface diffusion of silicon; in these conditions, adapted 2D arrays of trenches etched in Bulk Si are transformed into buried cavities creating suspended membranes. A 3D nanostructuration of silicon through hard mask engineering and high temperature annealing in hydrogen ambiance is reported. By using a nitride-oxide hard mask stack instead of a sacrificial oxide hard mask for a free surface (maskless) annealing, we open new technological and design possibilities using 2D arrays of various geometry trenches. Implications and potential device applications are discussed.
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R. Wacquez,
R. Cerutti,
P. Coronel,
A. Cros,
D. Fleury,
A. Pouydebasque,
J. Bustos,
S. Harrison,
N. Loubet,
S. Bborel,
D. Lenoble,
D. Delille,
F. Leverd, F. Judong,
M.P. Samson,
N. Vuillet,
B. Guillaumot,
T. Ernst,
P. Masson,
T. Skotnicki
International Conference on Solid State Devices and Materials (SSDM).
