Jae-Seung Lee

Pohang University of Science and Technology, Geijitsu, North Gyeongsang, South Korea

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Publications (7)5.3 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: A 3.8 Gb/s multi-drop single-ended integrating DFE (IDFE) receiver is implemented in a 0.18 um CMOS by using a single-loop LMS-algorithm to find the DFE coefficients automatically. Initially, a preamble input data pattern ('1101') is applied to the main IDFE circuit to determine the DFE coefficients, while a fixed input data pattern ('1111') is applied to the replica IDFE circuit. The difference between the outputs of the two IDFE circuits is used in the feedback loop to determine the DFE coefficients. The reference voltage (Vref) of preamplifier is generated inside chip by a Vref loop to reduce the effect of the external noise and the input offset voltage of preamplifier and IDFE circuits and also to track the mid-level of the input data swing in spite of process variations of TX chips. An integrating deskew scheme with a minimum overhead is introduced. 2-drop and 4-drop DRAM channels are tested. The maximum data rate was increased from 1.0 Gb/s to 2.6 Gb/s by DFE in the heavily loaded 4-drop interface, from 3.5 Gb/s to 3.8 Gb/s by DFE in the 2-drop interface.
    IEEE Journal of Solid-State Circuits 10/2011; · 3.06 Impact Factor
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    ABSTRACT: Recently, time amplifiers are used in time-to-digital converters(TDC) because the time resolution is better than the voltage resolution in modern integrated circuits. However, the conventional time amplifiers are limited in their time gain and input time difference range, because of their positive-feedback closed-loop architecture. An open-loop time amplifier is proposed in this work to achieve a large time gain up to 120 and a wide range of input time difference(10ps∼2ns). Besides, the time gain is the same as the current bias ratio. The worst-case average gain error which shows linear characteristics of the time amplifier is smaller than 5.3% The proposed time amplifier was successfully used in the monitoring circuit for threshold voltage variations of NMOS and PMOS FETs. The monitoring circuit consists of VCDL, time amplifier and TDC. The circuit was implemented by 0.13μm CMOS process.
    01/2011;
  • Jae-seung Lee, Jae-Yoon Sim, Hong-June Park
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    ABSTRACT: A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10µm and L = 0.18µm in a 16 × 16 array matrix fabricated with a 0.18-µm process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7mV and 32.2mV, respectively, for the temperature range from -25°C to 75°C. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10mV/bit and 3.53mV/bit at 25°C, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125ns, which corresponds to the 8-MHz throughput.
    IEICE Transactions. 01/2010; 93-C:1333-1337.
  • [Show abstract] [Hide abstract]
    ABSTRACT: A 2-Gb/s integrating decision-feedback equalization (DFE) receiver was implemented for a four-drop single-ended DRAM interface channel by using a 0.25- mum CMOS process. The receiver combines both DFE and integration operations in a single receiver circuit so that the DFE operation reduces the intersymbol interference and the integration operation reduces the high-frequency noise. The DFE operation was implemented by switching the capacitance values of the two output nodes of a differential integrator, depending on the previous decision data. A look-ahead scheme was used to reduce the DFE loop delay. A MUX-embedded D flip-flop was used in the look-ahead circuit to further reduce the DFE loop delay and latency. The DFE operation enhanced the voltage margins by 110% and 90% at the 2-Gb/s stubless channel and the 1.2-Gb/s stub series terminated logic channel, respectively. The chip area and the power dissipation of the proposed receiver chip were 220 times 120 mum<sup>2</sup> and 10 mW, respectively, at the data rate of 2 Gb/s.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 09/2009; · 2.24 Impact Factor
  • Source
    Jae-Seung Lee, Jae-Yoon Sim, Hong June Park
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    ABSTRACT: A systematic design guide for 3-stage CMOS operational amplifier (op amp) with nested Gm-C frequency compensation (NGCC) was proposed. With the given specification such as gain-bandwidth (GB), the ratio of high frequency pole to GB, phase margin, input common-mode range, and load capacitance, the guide generates the design parameters that minimize total area or current. The test chip designed by the proposed guide was fabricated with a 0.18-mum CMOS process. The simulation results show reasonable performances with 1.2-V supply voltage, and the measurement results show low-voltage operations of the designed op amps with 0.6-V supply voltage.
    SoC Design Conference, 2008. ISOCC '08. International; 12/2008
  • [Show abstract] [Hide abstract]
    ABSTRACT: A 3.2Gb/s single-ended current-integrating DFE receiver with 8b parallel data for 2-drop DRAM interface is implemented in a 0.18mum CMOS process. The reference voltage for the receiver is generated internally to reduce the external coupling noise. A single-loop implementation of sign-sign LMS algorithm is used to decide the single-tap equalization coefficient of the DFE receiver instead of the previous dual-loop implementation.
    Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International; 03/2008
  • Source
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    ABSTRACT: An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-C(NGCC) frequency compensation. The proposed design guide generates straight-forwardly the design parameters such as the W/L ratio and current of each transistor from the given design specifications, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The applications of this design guide to the two cases of 10pF and 100pF load capacitances, shows that the designed OP amp work with a reasonable performance in both cases, for the range of compensation capacitance from 10% to 100% of load capacitance.
    01/2006; 20(16).

Publication Stats

14 Citations
5.30 Total Impact Points

Institutions

  • 2006–2009
    • Pohang University of Science and Technology
      • • Department of Electronic and Electrical Engineering
      • • Department of Electrical and Computer Engineering
      Geijitsu, North Gyeongsang, South Korea