[show abstract][hide abstract] ABSTRACT: A method to laminate a thin monocrystalline Si layer to a conductive and fracture-resistant carrier such as steel has been developed, resulting in a practical design for high volume production of robust ultra-thin (10 -20 µm) "kerfless" Si wafers. With this technology front and rear cell features based on the world-record PERL cell design have been integrated. A confirmed efficiency of 15.1% has been achieved on a 20-micron thick one-cm 2 solar cell. This 15.1% is believed to be the highest confirmed efficiency achieved with ultra-thin silicon integrated with a conducting substrate.
[show abstract][hide abstract] ABSTRACT: Thin-film crystalline silicon (c-Si) solar cells have the potential for very high efficiency through high open circuit voltage (Voc) . The best performance reported in thin-film crystalline silicon solar cells with absorber thickness below 20 microns is 16.9% efficiency for a solar cell grown epitaxially on a crystalline silicon conductive substrate . The efficiency potential of thin c-Si solar cells is above 20%. In previously reported thin c-Si solar cells, layers of porous silicon have been included as a Bragg reflector in the light trapping design or as a separation layer in the mechanical design [3, 4]. The Bragg reflector uniformity and reliability has been analyzed . The challenges of this Bragg reflector are uniformity and the maximum achievable optical gain. This work presents a systematic approach to the design, fabrication, testing and analysis of thin c-Si solar cells. Solar cell designs presented include a thin c-Si solar cell with no light trapping structures and a thin c-Si solar cell with an optical design comprised of a metallic back reflector on the back surface and a chemical texture on the front surface. These baseline designs enable us to separately measure and localize voltage and current losses. The metallic back reflector has low electrical losses, good mechanical stability, and uniform optical properties. To optimize the baseline designs we measure open circuit voltage (Voc) and external quantum efficiency (EQE). Voc shows high material quality in the absorber layer. EQE shows an evidence of light trapping with a current gain of 3.6%.
[show abstract][hide abstract] ABSTRACT: The authors have presented a CMOS compatible method for the production and incorporation of NW arrays that may be a basis for future NWFETs and other NW based devices. This work also hints to the possibility of incorporating NWs of different semiconductor material onto the same substrate to achieve high performance FETs, LEDs, and other devices. The authors surmise that alternating layers of Ge and Si could produce stacked Ge NWs similar to the Si NW stacks in other work. Finally, the use of chemicals readily available to most fabrication facilities as well as the use of TMAH, to avoid the mobile ion contamination that can plaque other Si etchants, provides for a series of steps that could be incorporated into a CMOS facility.
Semiconductor Device Research Symposium, 2009. ISDRS '09. International; 01/2010
[show abstract][hide abstract] ABSTRACT: High Ge concentration Si:Ge solar cell based on low cost Si substrate fabricated by RTCVD can be applied in multi-junction solar cell system to absorb infrared light. First principle design shows that ideally Si:Ge solar cell with 90% Ge concentration can contribute 6.2% efficiency with 16.6mA/cm2 Jsc, 472mV Voc and 79.5% FF to a multi-junction solar cell system with a 300um silicon solar cell on its top under one sun. Under 50X suns, for the same multi-junction solar cell system, efficiency of bottom Si:Ge solar cell can reach to 7.8% with 574mV Voc, 82.2% FF. Modeling results show that for 90% Ge concentration Si:Ge solar cell, if optical thickness which is 8 times of its physical thickness can be achieved, Jsc can be 11.3mA/cm2, Voc of 462mV,and FF of 79.2%. In this case, under 50X sun efficiency an reach to 5.2% with 565mV Voc and 81.9% FF. Our initial Si:Ge solar cell without light trapping experimental results for 90%Ge with 5um absorber shows a Jsc of 5.76mA/cm2 with Si filter on top under one sun. For the same cell, Voc reaches to 205mV under 33X suns.
[show abstract][hide abstract] ABSTRACT: The development of Ge thin film substrates with low defect densities is of interest for future microelectronics as well as photovoltaics. This paper presents a complex x-ray characterization of Ge heterostructures, which were integrated on patterned Si(001) substrates using “aspect ratio trapping (ART)” and “epitaxial lateral overgrowth (ELO).” In both cases, thermal SiO <sub>2</sub> layers were patterned into trenches with appropriate aspect ratio to confine misfit dislocations. In the case of ART Ge thin films grown in 180 nm spaced trenches, the x-ray characterization reveals that the Ge coalescence process between neighboring growth windows must be carefully controlled to avoid defect generation. In the case of ELO Ge heterostructures grown from trenches spaced by 20 µm, coalescence effects are clearly reduced but complications are detected in the form of lattice plane tilt in the ELO wings. Simulations are applied to unveil the influence of the different thermal expansion coefficients of Ge, Si, and SiO <sub>2</sub> on the strain status of the ART and ELO Ge heterostructures.
Journal of Applied Physics 12/2009; · 2.21 Impact Factor
[show abstract][hide abstract] ABSTRACT: Thin Si solar cell with epitaxial lateral overgrowth (ELO) structure described in this paper should demonstrate higher voltage. PC-1D program has been used to study the open circuit voltage and efficiency as a function of the thin Si thickness and light trapping. According to the simulation results, high voltage can be obtained even without light trapping on the backside of the thin Si layer. Thin n type silicon layer has been grown on p+ Si substrate using the method of epitaxial lateral overgrowth by CVD. The scanning electron microscopy (SEM) has been used to show the dimension of the pn junction region and light generation region after the n type Si growth.
[show abstract][hide abstract] ABSTRACT: We describe the impact of Si substrate doping on the substrate leakage in strained Si two-dimensional electron gases (2DEG) on SiGe relaxed graded buffers and on quantum devices fabricated from the 2DEG. The best commercially available high quality SiGe relaxed buffers with 30% Ge content, grown at temperature above 1000^oC, have very low threading dislocation density (
[show abstract][hide abstract] ABSTRACT: High quality, low defect GaAs virtual substrates on Si, produced by the aspect ratio trapping growth technique, have been used for the fabrication of n<sup>+</sup>GaAs/n<sup>+</sup>InGaAs/p<sup>+</sup>GaAs Esaki diodes. All epitaxial layers were grown by reduced-pressure chemical vapor deposition/metalorganic chemical vapor deposition , instead of the molecular beam epitaxy technique commonly used for most high performance Esaki diodes. Four Esaki diode structures were fabricated and measured, with current densities up to 1 kA/cm<sup>2</sup>. Peak-to-valley current ratios up to 56 have been achieved, which is greater than twice that of the best GaAs Esaki diodes previously reported.
Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
[show abstract][hide abstract] ABSTRACT: Epitaxial GaAs layers have been deposited on polished Ge film grown on exactly (001) oriented Si substrate by metal-organic chemical vapor deposition (MOCVD) via aspect ratio trapping (ART) method. Double-crystal X-ray diffraction shows that the full-width at half-maximum (FWHM) of the (400) reflection obtained from 1μm GaAs is 140arcsec. Scanning electron microscopy (SEM) of the GaAs layer surface shows that the amount of antiphase domain defects (APD) raised from GaAs/Ge interface using Ge ART on Si is dramatically reduced compared to GaAs layers grown on exact (001) Ge substrate. Defect reduction and Ge diffusion at vicinal GaAs/Ge interface were investigated via cross-section transmission electron microscopy (X-TEM) and secondary ion mass spectrometry (SIMS). Film morphology and optical properties were evaluated via SEM and room temperature photoluminescence (PL).
Journal of Crystal Growth 01/2009; 311(11):3133-3137. · 1.55 Impact Factor
[show abstract][hide abstract] ABSTRACT: Recently much effort has been made in characterizing and realizing tunneling field effect transistors (TFET). Fundamental to the operation of such devices is the direct band-to-band tunneling of carriers from the n++ source to the p++ drain, which is the same current transport mechanism of Esaki Tunnel Diodes (ETD). Therefore, ETDs are an effective way to understand the potential of TFETs for high speed, low power applications. Few studies of submicron ETDs have been performed, which is critical for integration of TFETs into modern VLSI/UVLSI circuits. This paper reports on the fabrication and characterization of sub-micron GaAs/InGaAs ETDs on a Si substrate with junction areas below 0.1 ¿m2. Using conservative Jp, tunnel junctions of radii below 100 nm have been electrically tested. A semi-log plot of the forward and reverse I-V characteristics is shown. The reverse bias Zener currents show a range of 6 orders of magnitude. The large current devices show negative differential resistance, a result of using a large area ETD as a virtual ground. In the forward bias, peak currents (Ip) range 7 orders of magnitude.
[show abstract][hide abstract] ABSTRACT: Enhancement-mode (E-mode) n-channel InP metal-oxide-semiconductor field-effect-transistors (MOSFETs) with 0.75 to 40 mum gate length fabricated on semi-insulating substrates and p-type doped InP epi-layers with atomic-layer-deposited (ALD) Al<sub>2</sub>O<sub>3</sub> and HfO<sub>2</sub> as gate dielectrics are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high- quality gate oxides and unpinning of Fermi-level on compound semiconductors. A 1-mum gate-length E-mode n- channel MOSFET with a HfO<sub>2</sub> gate oxide thickness of 10 nm shows a maximum drain current of 130 mA/mm and a trans- conductance of 40 mS/mm at the highest gate bias of 6 V.
[show abstract][hide abstract] ABSTRACT: We report on the metallorganic chemical vapor deposition growth of GaAs on patterned Si (001) substrates, which utilizes the aspect ratio trapping method. It was found that when growing GaAs above the SiO <sub>2</sub> trenched region, coalescence-induced threading dislocations and stacking faults originated on top of the GaAs / SiO <sub>2</sub> interfaces. These defects were found to be indirectly related to the initial defect-trapping process during trenched GaAs growth. Causes of coalescence defect formation and its reduction were experimentally investigated by employing a two-step growth optimization scheme. Improvement of material quality has been characterized by cross-sectional and plan-view transmission electron microscopy and x-ray diffraction.
Journal of Applied Physics 06/2008; · 2.21 Impact Factor
[show abstract][hide abstract] ABSTRACT: This paper presents an extensive simulation study of a MOSFET with reverse embedded-SiGe (Rev. e-SiGe), a new strained-silicon concept that utilizes elastic relaxation of a buried compressive SiGe layer to induce tensile strain in the channel. Simulations were executed to calculate the channel stress for device structures with a gate length between 32 and 10 nm, and including 4900 different combinations of the device parameters. The device parameters most critical for determining the channel stress are identified, and it is shown that optimization of the device structure to maximize the channel stress can be understood in a simple manner involving only two underlying variables, the t<sub>SiGe</sub>/t<sub>Si</sub>; ratio and the silicon/SiGe island aspect ratio. A study of the practical limits to the critical determinants of channel stress is described, and the channel stress for optimized structures within these practical limits is simulated. The Rev. e-SiGe technique is shown to be effective, inducing a level of stress comparable to or exceeding conventional strained-silicon techniques, and it is shown to be scalable down to a gate length of 10 nm. An enhanced Rev. e-SiGe process is proposed involving spacer removal and gate recrystalization; simulations show that the enhanced process can nearly double the channel stress.
IEEE Transactions on Electron Devices 03/2008; · 2.06 Impact Factor
[show abstract][hide abstract] ABSTRACT: A Ge Esaki diode is demonstrated on Si atop a coalesced epitaxial layer of Ge grown through narrow openings in SiO<sub>2</sub> that are used to trap threading dislocations from the lattice mismatch. Spin-on doping was used to form the n-type junction and a controlled alloyed reaction of Al and Ge forms the p-type junction. At an alloy temperature of 580 C for 1 s, the Ge-on-Si diodes were found to have a peak-to-valley current ratio of 1.1 with a peak current density of 4.1 kA/cm<sup>2</sup>.
[show abstract][hide abstract] ABSTRACT: High quality GaAs epilayers grown by metal-organic chemical vapor deposition are demonstrated on a SiO2-patterned silicon substrate using aspect ratio trapping technique, whereby threading dislocations from lattice mismatch are largely reduced via trapping in SiO2 trenches during growth. A depletion-mode metal-oxide-semiconductor field-effect transistor (MOSFET) is demonstrated on a n-doped GaAs channel with atomic-layer deposited Al2O3 as the gate oxide. The 10 mu m gate length transistor has a maximum drain current of 88 mA/mm and a transconductance of 19 mS/mm. The surface mobility estimated from the accumulation drain current has a peak value of similar to 500 cm(2)/Vs, which is comparable with those from previously reported depletion-mode GaAs MOSFETs epitaxially grown on semi-insulating GaAs substrates.
[show abstract][hide abstract] ABSTRACT: Heterogeneous integration of high quality germanium and compound semiconductors onto large-size low-cost substrates holds great promise to improve the performance and functionality of silicon-based CMOS logic beyond Moore¿s Law, as well as to reduce the cost of compound semiconductor-based devices and circuits. In this article, the Aspect Ratio Trapping heteroepitaxy technique, a recently developed approach for integration of highly mismatched semiconductor materials, is presented. Its potential applications in Si-based CMOS, and in compound semiconductor-based electronics and optoelectronics device, are also discussed.