A. Lochtefeld

Rochester Institute of Technology, Rochester, NY, United States

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Publications (62)81.31 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: A metal–dielectric heterostructure that provides the combined capability of light trapping and surface passivation is reported. The light-trapping layer employs a porous aluminum anodic oxide (AAO) with metal nanoparticles formed in the pores on the rear surface of a thin crystalline silicon solar cell. Numerical finite-difference time domain (FDTD) simulations were performed to determine the pore diameter and spacing that would result in optimal light trapping for this metal-dielectric heterostructure. For a 2.5-μm-thick crystalline silicon device, the optimal pore diameter and spacing were determined to be ∼250 and ∼450 nm, respectively. These conditions resulted in an enhancement of the simulated photocurrent by ∼12.6% compared with a device in which the heterostructure was replaced with a homogenous aluminum oxide layer. Simulations also confirmed that the thickness of an underlying dielectric layer should be minimized to 10–20 nm, with the AAO barrier layer being maintained as thin as possible. Finally, it was shown that replacement of silver by aluminum in the pores resulted in a reduction in the photocurrent of 6.3% and would necessitate much larger pore spacing that is difficult to achieve experimentally and would result in thicker AAO barrier layers, which are undesirable.
    IEEE Journal of Photovoltaics 01/2014; 4(5):1212-1219. · 3.00 Impact Factor
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    ABSTRACT: A method to laminate a thin monocrystalline Si layer to a conductive and fracture-resistant carrier such as steel has been developed, resulting in a practical design for high volume production of robust ultra-thin (10 -20 µm) "kerfless" Si wafers. With this technology front and rear cell features based on the world-record PERL cell design have been integrated. A confirmed efficiency of 15.1% has been achieved on a 20-micron thick one-cm 2 solar cell. This 15.1% is believed to be the highest confirmed efficiency achieved with ultra-thin silicon integrated with a conducting substrate.
    39th IEEE Photovoltaics Specialists Conference 2013, Tampa, Florida; 06/2013
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    ABSTRACT: In this paper, we fabricate and analyze thin silicon solar cells that are designed to have an increased voltage due to reduced junction area. This reduced junction area is achieved by using epitaxial lateral overgrowth to grow an n-Si photon absorber on a p+ Si substrate. We measure and analyze the voltage of these solar cells as a function of the junction area but find that the voltage does not demonstrate the expected gain with the reduced area. Scanning electron microscopic (SEM) cross sections indicate that the loss in voltage arises mainly from the poor quality of the lateral overgrowth region. Thus, future work will focus on improving this region's quality.
    IEEE Journal of Photovoltaics 01/2013; 3(1):119-124. · 3.00 Impact Factor
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    ABSTRACT: We have investigated the microstructure and device characteristics of GaAs0.82P0.18 solar cells grown on Si0.20Ge0.80/Si graded buffers. Anti-phase domains (APDs) were largely self-annihilated within the In0.39Ga0.61P initiation layer although a low density of APDs was found to propagate to the surface. A combination of techniques was used to show that the GaAs0.82P0.18 cells have a threading dislocation density of 1.2 ± 0.2 × 107 cm-2. Despite these extended defects, the devices exhibited high open-circuit voltages of 1.10–1.12 V. These results indicate that cascading a GaAs0.82P0.18 top cell with a lower-bandgap Si0.20Ge0.80 cell is a promising approach for high-efficiency dual-junction devices on low-cost Si substrates.
    Applied Physics Letters 01/2013; 103(19):191901. · 3.79 Impact Factor
  • Yi Wang, A. Gerger, A. Lochtefeld, R. Opila, A. Barnett
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    ABSTRACT: A light trapping design which increases the effective optical path length by a factor of 21 is designed for Ge:Si solar cell. Experimental results achieved an increase in effective optical path length of 17X which led to a Jsc of 7.91mA/cm2 for 88%Ge content Ge:Si solar cell below Si at one sun. Jsc is 120% higher than that of solar cells without light trapping. Below Si at 30 suns, the efficiency of 88%Ge content Ge:Si solar cell with light trapping reached 1.37% which is 60% of the theoretical efficiency maximum.
    Photovoltaic Specialists Conference (PVSC), 2012 38th IEEE; 01/2012
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    ABSTRACT: This paper introduces the modeling developed to assess the potential of a III-V/SiGe tandem device. Demonstration of value will be executed via materials and solar cell device models. III-V top cell candidates are evaluated and a high-value composition is identified. Initial windowless GaAsP solar cells demonstrate a bandgap-voltage offset of 0.58.
    Photovoltaic Specialists Conference (PVSC), 2012 38th IEEE; 01/2012
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    ABSTRACT: A 3-terminal Si-Si:Ge tandem solar cell, which consists of a top silicon solar cell and a bottom Si:Ge solar cell sharing a common base, has been designed and fabricated. This solar cell is designed to replace standalone Si solar cell and Si:Ge solar cell in a multi-junction solar cell system in order to simplify the module, improve its performance and reduce its cost. Initial results show that both Si solar cells and Si:Ge solar cells in this structure can achieve good performance. The best Si solar cell shows a Voc 598.5mV, Jsc 22.9mA/cm2 and FF 77.3% under one sun, best Si:Ge solar cell shows a Voc 189mV and Jsc 3.26mA/cm2 below silicon filter. None of these solar cells have anti-reflection coatings.
    Photovoltaic Specialists Conference (PVSC), 2011 37th IEEE; 01/2011
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    ABSTRACT: Low band gap germanium:silicon (Ge:Si) solar cells for operation with a silicon solar cell in a multi-junction concentrator system was designed, fabricated, characterized and analyzed. First principle simulations show that an efficiency of 2.3% can be achieved for 88% Ge concentration Ge:Si solar cells below Si at 30 suns. Through solving critical shunting and open circuit voltage (Voc) problems, an efficiency of 0.79% with a Voc of 350 mV and a fill factor (FF) of 66% was achieved for our third generation Ge:Si solar cells below Si at 30 suns.
    Photovoltaic Specialists Conference (PVSC), 2011 37th IEEE; 01/2011
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    ABSTRACT: Epitaxial lateral overgrowth (ELO) has been used to achieve a reduced p-n junction area for thin Si solar cells with the goal of achieving increased voltage. The n-Si absorber is grown by ELO on the p+ Si substrate. In this work, a novel ELO mask is designed, in which the effects of different factors on the voltage can be analyzed separately. The mask design starts from a basic ELO solar cell structure, where there is only one p-n junction. With this structure, the factors that can be studied include the light generation area to p-n junction area ratio, orientation of the growth layer, geometry of the p-n junction and the dielectric material. The second structure has two p-n junctions, with coalescent Si layer resulting from the ELO. The voltage of the selective planar cells has been analyzed first in this work. It shows that the lateral overgrowth region may have a poor quality that results in a loss in open circuit voltage (Voc) and fill factor (FF). The analysis in this work will be the guidance for the future ELO reduced junction thin Si solar cells.
    Photovoltaic Specialists Conference (PVSC), 2011 37th IEEE; 01/2011
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    ABSTRACT: Thin-film crystalline silicon (c-Si) solar cells have the potential for very high efficiency through high open circuit voltage (Voc) [1]. The best performance reported in thin-film crystalline silicon solar cells with absorber thickness below 20 microns is 16.9% efficiency for a solar cell grown epitaxially on a crystalline silicon conductive substrate [2]. The efficiency potential of thin c-Si solar cells is above 20%. In previously reported thin c-Si solar cells, layers of porous silicon have been included as a Bragg reflector in the light trapping design or as a separation layer in the mechanical design [3, 4]. The Bragg reflector uniformity and reliability has been analyzed [5]. The challenges of this Bragg reflector are uniformity and the maximum achievable optical gain. This work presents a systematic approach to the design, fabrication, testing and analysis of thin c-Si solar cells. Solar cell designs presented include a thin c-Si solar cell with no light trapping structures and a thin c-Si solar cell with an optical design comprised of a metallic back reflector on the back surface and a chemical texture on the front surface. These baseline designs enable us to separately measure and localize voltage and current losses. The metallic back reflector has low electrical losses, good mechanical stability, and uniform optical properties. To optimize the baseline designs we measure open circuit voltage (Voc) and external quantum efficiency (EQE). Voc shows high material quality in the absorber layer. EQE shows an evidence of light trapping with a current gain of 3.6%.
    Conference Record of the IEEE Photovoltaic Specialists Conference 01/2011;
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    ABSTRACT: The authors have presented a CMOS compatible method for the production and incorporation of NW arrays that may be a basis for future NWFETs and other NW based devices. This work also hints to the possibility of incorporating NWs of different semiconductor material onto the same substrate to achieve high performance FETs, LEDs, and other devices. The authors surmise that alternating layers of Ge and Si could produce stacked Ge NWs similar to the Si NW stacks in other work. Finally, the use of chemicals readily available to most fabrication facilities as well as the use of TMAH, to avoid the mobile ion contamination that can plaque other Si etchants, provides for a series of steps that could be incorporated into a CMOS facility.
    Semiconductor Device Research Symposium, 2009. ISDRS '09. International; 01/2010
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    ABSTRACT: The value of a high performance thin silicon solar cell is based on high open circuit voltage (Voc) which is highly dependent upon surface and interface recombination. A microelectronic approach with the series and parallel fabrication of different device structures is presented. This approach includes the fabrication of planar solar cells based on different solar cell designs that maximize Voc. Subsequently, using the same solar cell design, more advanced epitaxial growth test structures were fabricated on the same substrate to understand recombination losses and Voc. In high performance thin silicon solar cells, Voc is highly sensitive to surface recombination. Achieving a good surface and interface passivation in epitaxial silicon solar cells is a challenge, especially for the absorber back surface. In this work, we used test structures embedded in the solar cells to independently optimize Voc and the back surface of a thin epitaxial absorber as well as other silicon interfaces. Most epitaxial thin silicon solar cells are fabricated with in-situ processes that lead to difficulties in the independent optimization of such surfaces. To contribute to the design space in thin silicon solar cells, we tested basic device designs and test structures that lead to high Voc. The design of basic structures is important to measure parameters that limit voltage. This is a diagnostic tool for the fabrication of high performance thin silicon solar cells. This work reports device results that exhibit a path to high open circuit voltage, determined by device design, interface recombination, and bulk lifetime. With independent optimization of parameters that limit Voc and therefore performance, this work contributes to the understanding of thin silicon solar cells.
    Photovoltaic Specialists Conference (PVSC), 2010 35th IEEE; 01/2010
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    ABSTRACT: Thin silicon (Si) solar cells have the potential of having high performance due to lower bulk recombination which leads to high open circuit voltage. It has been reported that the potential advantages of n type Si include longer lifetime, easier surface passivation, and no light-induced performance degradation. Therefore, a thin Si solar cell structure based on n type absorber is an important area to investigate for higher performance. Thin Si solar cells based on epitaxial lateral overgrowth (ELO) of the n type absorber have been previously reported. Open circuit voltage (Voc) is expected to be improved from utilizing an ELO solar cell due to reduced p-n junction area, which leads to a decrease in the dark saturation current. In this work, planar thin Si solar cells based upon n type epitaxial absorber have been fabricated and initial solar cell results have been analyzed. The processing steps developed for the planar solar cells will be transferred to the ELO solar cells. For the ELO solar cells, a more informative set of patterns have been designed, including different light generation area (AL) to p-n junction area (A0) ratios, different line orientations and different test patterns. PC1D software has been used to investigate the Voc and efficiency as a function of n type and p type Si absorber thickness, respectively.
    Photovoltaic Specialists Conference (PVSC), 2010 35th IEEE; 01/2010
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    ABSTRACT: High Ge concentration Si:Ge solar cell based on low cost Si substrate fabricated by RTCVD can be applied in multi-junction solar cell system to absorb infrared light. First principle design shows that ideally Si:Ge solar cell with 90% Ge concentration can contribute 6.2% efficiency with 16.6mA/cm2 Jsc, 472mV Voc and 79.5% FF to a multi-junction solar cell system with a 300um silicon solar cell on its top under one sun. Under 50X suns, for the same multi-junction solar cell system, efficiency of bottom Si:Ge solar cell can reach to 7.8% with 574mV Voc, 82.2% FF. Modeling results show that for 90% Ge concentration Si:Ge solar cell, if optical thickness which is 8 times of its physical thickness can be achieved, Jsc can be 11.3mA/cm2, Voc of 462mV,and FF of 79.2%. In this case, under 50X sun efficiency an reach to 5.2% with 565mV Voc and 81.9% FF. Our initial Si:Ge solar cell without light trapping experimental results for 90%Ge with 5um absorber shows a Jsc of 5.76mA/cm2 with Si filter on top under one sun. For the same cell, Voc reaches to 205mV under 33X suns.
    Conference Record of the IEEE Photovoltaic Specialists Conference 01/2010;
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    ABSTRACT: The development of Ge thin film substrates with low defect densities is of interest for future microelectronics as well as photovoltaics. This paper presents a complex x-ray characterization of Ge heterostructures, which were integrated on patterned Si(001) substrates using “aspect ratio trapping (ART)” and “epitaxial lateral overgrowth (ELO).” In both cases, thermal SiO <sub>2</sub> layers were patterned into trenches with appropriate aspect ratio to confine misfit dislocations. In the case of ART Ge thin films grown in 180 nm spaced trenches, the x-ray characterization reveals that the Ge coalescence process between neighboring growth windows must be carefully controlled to avoid defect generation. In the case of ELO Ge heterostructures grown from trenches spaced by 20 µm, coalescence effects are clearly reduced but complications are detected in the form of lattice plane tilt in the ELO wings. Simulations are applied to unveil the influence of the different thermal expansion coefficients of Ge, Si, and SiO <sub>2</sub> on the strain status of the ART and ELO Ge heterostructures.
    Journal of Applied Physics 12/2009; · 2.21 Impact Factor
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    ABSTRACT: Thin Si solar cell with epitaxial lateral overgrowth (ELO) structure described in this paper should demonstrate higher voltage. PC-1D program has been used to study the open circuit voltage and efficiency as a function of the thin Si thickness and light trapping. According to the simulation results, high voltage can be obtained even without light trapping on the backside of the thin Si layer. Thin n type silicon layer has been grown on p+ Si substrate using the method of epitaxial lateral overgrowth by CVD. The scanning electron microscopy (SEM) has been used to show the dimension of the pn junction region and light generation region after the n type Si growth.
    Photovoltaic Specialists Conference (PVSC), 2009 34th IEEE; 07/2009
  • Journal of The Electrochemical Society. 06/2009; 156(7):H574-H578.
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    ABSTRACT: We describe the impact of Si substrate doping on the substrate leakage in strained Si two-dimensional electron gases (2DEG) on SiGe relaxed graded buffers and on quantum devices fabricated from the 2DEG. The best commercially available high quality SiGe relaxed buffers with 30% Ge content, grown at temperature above 1000^oC, have very low threading dislocation density (
    03/2009;
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    ABSTRACT: High quality, low defect GaAs virtual substrates on Si, produced by the aspect ratio trapping growth technique, have been used for the fabrication of n<sup>+</sup>GaAs/n<sup>+</sup>InGaAs/p<sup>+</sup>GaAs Esaki diodes. All epitaxial layers were grown by reduced-pressure chemical vapor deposition/metalorganic chemical vapor deposition , instead of the molecular beam epitaxy technique commonly used for most high performance Esaki diodes. Four Esaki diode structures were fabricated and measured, with current densities up to 1 kA/cm<sup>2</sup>. Peak-to-valley current ratios up to 56 have been achieved, which is greater than twice that of the best GaAs Esaki diodes previously reported.
    Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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    ABSTRACT: Recently much effort has been made in characterizing and realizing tunneling field effect transistors (TFET). Fundamental to the operation of such devices is the direct band-to-band tunneling of carriers from the n++ source to the p++ drain, which is the same current transport mechanism of Esaki Tunnel Diodes (ETD). Therefore, ETDs are an effective way to understand the potential of TFETs for high speed, low power applications. Few studies of submicron ETDs have been performed, which is critical for integration of TFETs into modern VLSI/UVLSI circuits. This paper reports on the fabrication and characterization of sub-micron GaAs/InGaAs ETDs on a Si substrate with junction areas below 0.1 ¿m2. Using conservative Jp, tunnel junctions of radii below 100 nm have been electrically tested. A semi-log plot of the forward and reverse I-V characteristics is shown. The reverse bias Zener currents show a range of 6 orders of magnitude. The large current devices show negative differential resistance, a result of using a large area ETD as a virtual ground. In the forward bias, peak currents (Ip) range 7 orders of magnitude.
    01/2009;

Publication Stats

806 Citations
81.31 Total Impact Points

Institutions

  • 2008–2010
    • Rochester Institute of Technology
      • Department of Electrical and Microelectronic Engineering
      Rochester, NY, United States
  • 2009
    • Institute for High Performance Microelectronics
      Frankfort on the Oder, Brandenburg, Germany
  • 2007–2008
    • Purdue University
      • School of Electrical and Computer Engineering
      West Lafayette, IN, United States
  • 1996–2004
    • Massachusetts Institute of Technology
      • Department of Electrical Engineering and Computer Science
      Cambridge, Massachusetts, United States