ABSTRACT: Highest planar HK/MG PFET performance (I<sub>ON</sub> = 790 muA at I<sub>off</sub> = 100 nA, Vdd= 1 V and Lg= 33 nm) has been demonstrated with a gate-first dual-metal CMOS integrated process and proven by functional SRAM cell. Integrating modern stressors without IL re-growth and achieving band edge work function without increasing T<sub>INV</sub> are two major challenges for gate-first HK/MG processes. In this work, band-edge effective work function has been achieved without increasing T<sub>INV</sub>. Furthermore, with successful integration of stress techniques like SiGe-S/D, SMT and CESL, not only performance was improved by 30% but also no reliability degradation was observed. Finally, no degradation from decreasing poly-pitch also suggests its good scalability to next generations.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008