R. Delhougne

imec Belgium, Louvain, Flanders, Belgium

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Publications (32)37.86 Total impact

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    ABSTRACT: In this article we use a novel method to assess the retention properties of a PCM line cell having a fast-growth chalcogenide material. We monitor the cell resistance during temperature-ramp experiments carried out after reset programming of the cells. The temperature-dependent resistance is modeled assuming the crystallization proceeds by the crystal growth of the amorphous/crystal interfacial front. The results show good reproducibility, excellent match with the measurements, and consistency with investigations using isothermal experiments. For a single temperature-ramp experiment this fast method allows the extraction of the activation energy for growth as well as the extrapolated temperature for 10 years retention lifetime. We use the method to investigate the influence of the length and thickness of the programmed amorphous mark on the retention lifetime. The results point to improved retention for thicker and longer amorphous marks, however the extrapolation of the results down to short marks suggests a limited reduction of the retention lifetime with the cell downscaling.Research highlights► We model the temperature-dependent resistance of a fast-growth phase-change cell. ► We obtain excellent match assuming crystal growth from the amorphous/crystal front. ► A single temperature ramp allows the extraction of retention characteristics. ► Using this method we predict a limited lifetime reduction with cell downscaling.
    Solid-State Electronics 01/2011; 58(1):17-22. · 1.48 Impact Factor
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    ABSTRACT: In this letter, we propose a novel method for the extraction of the crystal-growth parameters as a function of temperature in a reset-programmed phase-change memory cell having fast-growth chalcogenide material. The activation energy for the growth of crystal front is obtained using a physics-based analytical simulation fitting a single temperature-ramp measurement. The fit relies on all data points of the ramp measurement, allowing fast and precise determination of the activation energy related to the retention loss of the memory cell.
    IEEE Electron Device Letters 12/2010; · 2.79 Impact Factor
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    ABSTRACT: Junction leakage becomes more significant as metal-oxide-semiconductor (MOS) technologies scale down in bulk-silicon. In this work we quantify the four key elements to junction leakage generation through a combination of experiment and device simulation. These elements are: (i) ultra-shallow junction steepness, (ii) channel and pocket concentrations, (iii) junction curvature, and (iv) the presence of residual defects. We first characterize n+/p and p+/n diodes to quantify how changes in doping profiles affect reverse bias leakage. Diodes with end-of-range (EOR) silicon defects intentionally located in the junction depletion region are also characterized to quantify their contribution. This feeds into a device simulation study to gain insight in the experimental results and in the capabilities of available physical models. Thereafter simulation is used to predict leakage in future generation bulk-silicon MOS devices. In summary, band-to-band tunneling (BBT) due to aggressively scaled doping profiles and trap-assisted tunneling (TAT) due to the increased presence of defects make off-state low-standby-power leakage targets difficult to meet. With the increase of junction leakage from aggressively scaled ultra-shallow junctions, the assumption that the subthreshold leakage component dominates off-state current is no longer valid.
    Solid-State Electronics 01/2010; 54(3):243-251. · 1.48 Impact Factor
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    ABSTRACT: In this work we propose a novel method for fast and reliable evaluation of the retention properties of phase-change memory cells, based on the modeling of the temperature-ramp characteristics. Using this method we investigate the influence of the length and thickness of the amorphous mark on the retention lifetime. The results show that the degradation of the retention properties with the cell scaling is limited.
    01/2010;
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    ABSTRACT: We report on successful array level integration of a Phase Change Random Access Memory (PCRAM) with a narrow line of doped-Sb2Te phase change material, embedded in a standard 65nm CMOS process. Demonstrator cells can be reversibly reprogrammed between two well-defined resistance levels and correlate well with data achieved on megabit array level. The low process complexity, standard back-end temperature budget and ease of integration combined with the low voltage and current operation makes this line concept highly suitable for embedded PCRAM applications.
    Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International 01/2010;
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    ABSTRACT: In this paper, we investigate the effect of the reset-pulse parameters of a phase-change memory line cell on the electrical cell properties. By means of electrothermal finite-element simulations and measurements, the characteristics of the reset state (resistance after switching, threshold voltage, and stability of the state) are related to the physical parameters during reset switching (the temporal and spatial distribution of the temperature during switching, the evolution of the melting and molten phases, and the time that the line is molten). From a device point of view, we emphasize the following aspects: 1) Due to good thermal isolation, the line cell can be reset using a 5-ns short current pulse of limited amplitude; 2) longer pulsewidths allow lower reset current amplitudes due to the gradual heating of surrounding dielectric; 3) the reset resistance has no direct relation with the threshold voltage but is strongly related to the number of reset pulses applied to the cell; and 4) shorter pulsewidths allow extended endurance lifetimes.
    IEEE Transactions on Electron Devices 08/2009; · 2.06 Impact Factor
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    ABSTRACT: In this brief, we studied the endurance properties of an integrated phase-change line cell. The different characteristics typically observed during the endurance lifetime are described. The monitoring of the switching parameters of the cell (reset current and threshold voltage) during endurance testing could be correlated with a gradual degradation of the reset switching. The following conclusions were drawn: 1) The reset-switching degradation is closely associated to both an increase of the minimum reset current and a decrease of the obtained reset and set resistances, pointing to material change; 2) the extent of the degradation strongly depends on the reset pulsewidth, and it was found to scale with tm <sup>3/2</sup>, tm being the melting time during reset pulse; however, higher reset currents did not quicken the onset of degradation; and 3) the tm <sup>3/2</sup> dependence together with polarity-dependent endurance tests suggests the contribution of an electrical-field-driven migration mechanism. Based on these insights, the extended endurance lifetime of more than 10<sup>10</sup> cycles could be demonstrated, using short reset pulses, which could be further increased by changing reset polarity before stuck-set failure.
    IEEE Transactions on Electron Devices 03/2009; · 2.06 Impact Factor
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    ABSTRACT: For phase change random access memory applications, the scaling perspective of the 3 main programming parameters is essential. The programming time will largely determine the obtainable data rate. The required programming current will largely determine the transistor size and hence the obtainable memory density. Finally, the programming voltage should preferably not exceed the transistor driving voltage. In this paper, the scaling perspective for these 3 main programming parameters is investigated for doped Sb<sub>2</sub>Te PCRAM line cells.
    Non-Volatile Semiconductor Memory Workshop, 2008 and 2008 International Conference on Memory Technology and Design. NVSMW/ICMTD 2008. Joint; 06/2008
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    ABSTRACT: The resistive-switching phase-change memory (PCM) is gaining increasing interest as a potential flash replacement, mainly due to scalability, faster writing and better endurance. PCM cells are typically programmed to the high- resistive amorphous state using a high current pulse (reset programming), and to the low-resistive crystalline state using a longer pulse of lower amplitude (set programming). The parameters considered to mainly control reset switching are the reset current I<sub>R</sub>, sufficiently high to reach the melt temperature T<sub>m</sub> of the PCM material, and the quench time t<sub>q</sub>, short enough to freeze-in the melt state. The optimization of these parameters, as demonstrated for Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub>-based vertical cells in the literature (D. Mantagazza et al., 2006), (T. Nirschi et al., 2007), is thus a key to better control the switching of the cell. In the present work the influence of the pulse parameters on the reset state is investigated for a SbTe-based lateral cell. A new phenomenon affecting the resistance of the amorphous phase after reset is identified and a strong influence of the time-under-melt parameter is demonstrated.
    Non-Volatile Semiconductor Memory Workshop, 2008 and 2008 International Conference on Memory Technology and Design. NVSMW/ICMTD 2008. Joint; 06/2008
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    ABSTRACT: We present physical and electrical evidence of the Thomson thermo-electric effect in line-type phase-change memory cells. This causes a shift of the molten zone during RESET programming towards the anode contact, and as a consequence the phase change material (PCM) design at the contact area has a significant influence on the program conditions. First statistical studies showed a reduction of minimum Reset currents by ~5% and Set voltages by -28% when PCM extensions around the anode are used instead of fine line contacts. This Thomson effect remains important with further cell scaling.
    Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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    ABSTRACT: The structural reaction of sub- and supercritical thickness-strained Si layers on novel thin SiGe strain-relaxed buffers (SRBs) during high-temperature annealing used in device fabrication is investigated. Atomic force microscopy, chemical defect etching, scanning electron microscopy, optical profilometry, optical microscopy, and Raman spectroscopy are used to study defect formation and morphology on thin and thick Si(0.82)Ge(0.18) SRBs grown using a C-induced relaxation technique. For subcritical thickness layers, the defect density was found to be similar in both thin and thick SRBs and both structures responded similarly to annealing, indicating good thermal stability of thin SRB technology. The root-mean-square surface roughness of strained Si grown on thin SRBs was similar to 50% lower than on similarly grown thick SRBs and conventional step-graded thick SRBs, and was robust during annealing. The impact of strained Si layer thickness on surface morphology is also analyzed. Using detailed filtering techniques, macro- and microroughness are distinguishable. For the first time, we show that exceeding the critical thickness has a greater impact on microroughness than on macroroughness. Whereas macroroughness is similar for sub- and supercritical thickness-strained Si layers, the microroughness is similar to 2x larger in supercritical layers than in subcritical thickness layers. Prominent surface defects were detected on supercritical strained Si layers. The defects align with the cross-hatch morphology and double in density following annealing. It is proposed that the defects originate from localized threading dislocations assisted by further strain relaxation in the metastable strained Si layers. This is substantiated through the observation of stacking faults in the strained Si. In contrast, surfaces of subcritical thickness-strained Si layers on thin SRBs are defect-free. (c) 2007 American Institute of Physics.
    Journal of Applied Physics 01/2007; 102(12). · 2.21 Impact Factor
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    ABSTRACT: Carrier illumination is an optical, fast, and nondestructive technique for an ultrashallow complementary metal oxide semiconductor structure characterization based on the measurement of differential probe laser reflectivity changes, which originate from refractive index variations induced by excess carriers generated by a second modulated pump laser. By changing the pump laser power it is possible to influence the depth of the main internal reflection and thus to sense the shape of the underlying electrically active profile. The extraction of the latter is, however, critically dependent on our in-depth physical understanding of the underlying processes. In this work, recent progress will be discussed with respect to the improved physical modeling of the generation-recombination processes (SRH, Auger, indirect phonon absorption, and free carrier absorption), mobilities, impact of temperature (heating by the lasers), and influence of slow surface state traps (time dependent behavior). In order to quantify the contribution of each parameter in the power curves (representing the probe reflectivity signal versus the pump power), three-dimensional axisymmetric numerical device simulations have been performed. These simulations will be compared to experimental data for a variety of structures (bulk material and chemical vapor deposition grown layers).
    Journal of vacuum science & technology. B, Microelectronics and nanometer structures: processing, measurement, and phenomena: an official journal of the American Vacuum Society 06/2006; · 1.27 Impact Factor
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    ABSTRACT: This paper describes the impact of various defect types on the junction leakage in highly doped drain junctions, fabricated on strained silicon/relaxed silicon–germanium virtual substrates. The substrates were fabricated with a thin buffer-layer scheme, using a carbon-doped layer to induce a high relaxation degree of the virtual substrate. Threading dislocations, carbon-induced defects, and residual implantation damage each have a distinct effect on the junction leakage, generation lifetime, and high-temperature behavior of the diodes. It is shown that threading dislocations degrade the junction quality at room temperature. However, the high-temperature behavior of these junctions is diffusion-dominated. When present in the depletion region, carbon-induced defects cause a large generation current inside the diodes, a behavior that is dominant in the full temperature range investigated . Implantation damage influences the leakage in silicon junctions but is of minor importance in junctions with a large amount of threading dislocations or carbon-induced defects. While increasing the thermal anneal budget has a large relative influence on the silicon junctions, this effect is less pronounced for the junctions, showing that defects associated with threading dislocations or carbon-induced defects are not as easily removed as damage resulting from the n-well implantation.
    Journal of The Electrochemical Society. 04/2006; 153(5):G379-G384.
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    ABSTRACT: In this work, the impact of high temperature annealing typical of CMOS processing on the surface morphology of thin SiGe SRBs is investigated for strained silicon layers above and below the critical thickness
    01/2006;
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    01/2006: pages 65-70;
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    ABSTRACT: As an economically more attractive alternative to the classical thick graded strain-relaxed SiGe Buffer layers (SRB), we have developed a thin SRB based on a 200-nm-thick homogeneous Si0.8Ge0.2 layer with a C-doping spike inserted in about the middle of the layer. This C-doping layer enhances strongly the relaxation of the layer to ∼80%, when compared to samples without C layer. The thin SRB shows threading defect densities ≤107/cm2 and a very smooth surface (RMS
    Thin Solid Films 01/2006; 508(1):260-265. · 1.60 Impact Factor
  • Roger Loo, Romain Delhougne, Matty Caymax, Mike Ries
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    ABSTRACT: Misfit dislocations at the strained Si/SiGe strain-relaxed buffer interface are known to enhance leakage currents of strained Si metal oxide semiconductor devices. As we show in this letter, misfit dislocations at this interface might be generated even for Si thicknesses below the critical thickness for layer relaxation. The important parameter is the degree of relaxation of the strain-relaxed buffer. If the strain-relaxed buffer is not fully relaxed, threading dislocations can glide during thermal treatments. This results in misfit dislocations at the strained Si/SiGe interface, because the threading dislocation segments within the strained Si are blocked by its tensile stress.
    Applied Physics Letters 10/2005; 87(18):182108-182108-3. · 3.79 Impact Factor
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    ABSTRACT: This paper describes the low-frequency noise behaviour of n-MOSFETs, fabricated in different types of strained-silicon (SSi) substrates. It is shown that compared with standard silicon devices, both a lower and a higher LF noise can be obtained for long-channel (L=1μm) transistors. The noise reduction is ascribed to the inherently better Si-SiO<sub>2</sub> interface quality on a tensile-strained silicon substrate. The higher noise has been found in components were it is believed that the strain is completely relaxed, giving rise to extended defects near the active device regions and an associated excess generation-recombination noise component. It will finally be shown that the better noise performance on SSi substrates may become lost for shorter channel lengths (L=0.15 μm), due to the dominance of random telegraph signal fluctuations.
    Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 10/2005
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    ABSTRACT: A set of direct techniques were combined to resolve the carrier recombination, trapping and diffusion parameters in thin strain-relaxed SiGe buffer (SRB) layers in a contact-less way. The excess carrier density relaxation in a wide time scale from picoseconds to tens of microseconds was examined by the microwave absorption/reflection and light-induced reflection/grating transients. A decrease of recombination lifetime in nanosecond-time scale as a function of threading dislocations (TD) density was determined. The asymptotic hyperbolic-like carrier decay in the SRBs was ascribed to multi-trapping processes characterized by trapping coefficients Ktr > 10. Relaxation of multi-trapping in the disordered structure of the dislocation-rich SRBs was generalized by the stretched-exponent approach. The time-stretching index of 0.15 was found to be the same for dislocation-rich SRBs, containing different densities of TDs. Value of the lateral carrier ambipolar diffusion coefficient Da ≤ 0.13 cm2 s−1 was estimated. Peculiarities of the J–V characteristics of diodes fabricated in the SRBs were examined and attributed to the space charge limitation effects. These features correlate with carrier trapping and slow diffusion unveiled by transient techniques.
    Semiconductor Science and Technology 09/2005; 20(10):1052. · 1.92 Impact Factor
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    ABSTRACT: The low-frequency (LF) noise behavior of n-MOSFETs fabricated on strained silicon (SSi) substrates is described and compared with the results obtained on devices in standard silicon wafers. It is demonstrated that a significant lowering (up to a factor 3) of the 1/f noise can be achieved. This improvement is shown correlated with the higher inversion-layer mobility μ0 and is believed to have a common origin, namely, the biaxial tensile strain in the thin silicon epitaxial layer. This improves the quality of the gate oxide, resulting in lower trapping and Coulombic scattering and, hence, in a better 1/f noise performance.
    08/2005;