[Show abstract][Hide abstract] ABSTRACT: Axially doped p–n silicon nanowire (SiNW) gated diodes are fabricated, and their electrical properties are investigated to demonstrate the enhanced surface effects on the nanoscale devices of semiconductor nanomaterials. The fabricated p–n SiNW exhibited clear rectifying characteristics with an ideality factor of 2. More interestingly, the gated p–n SiNW showed a switching behavior as a function of the gate bias with almost complete turn-off of the forward current. The observed ideality factor and gated diode characteristics were explained with surface trap states of the nanowires. Systematic 3D device simulation quantitatively confirms that the surface states are a key factor in determining such surface-dominated characteristics. This work would serve the fundamental and in-depth understanding of the surface properties in the various nanoscale 1D devices.
The Journal of Physical Chemistry C 11/2011; 115(47). DOI:10.1021/jp206639b · 4.77 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Electrical characteristics of multi bridged channel field effect transistor (MBCFET) with various channel lengths (L) ranging from 500 to 48 nm have been investigated. The current--voltage characteristics do not show any sign of short channel effect due to surrounding gate structures. The gate bias power law of the drain saturation current, mobility, and ballistic efficiency as functions of L show mixed features of drift-diffusion and ballistic transport. The channel resistance shows anomalous decrease when L
Japanese Journal of Applied Physics 04/2011; 50(4). DOI:10.1143/JJAP.50.04DC18 · 1.13 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Temperature-dependent electrical transport measurements of cylindrical shaped gate-all-around silicon nanowire p-channel MOSFET were performed. At 4.2 K, they show current oscillations, which can be analyzed by single hole tunneling originated from nanowire quantum dots. In addition to this single hole tunneling, one device exhibited strong current peaks, surviving even at room temperature. The separations between these current peaks corresponded to the energy of 25 and 26 meV. These values were consistent with the sum of the bound-state energy spacing and the charging energy of a single boron atom. The radius calculated from the obtained single-atom charging energy was also comparable to the light-hole Bohr radius.
IEEE Transactions on Nanotechnology 12/2009; DOI:10.1109/TNANO.2009.2021844 · 1.83 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The mobility-degradation factor and the series resistance of cylindrical gate-all-around silicon nanowire field-effect transistors are extracted using the same mobility-degradation model as in the case of planar MOSFETs. The extraction is done by defining an asymptotic voltage as a function of the saturation current measured from devices with various lengths. The extracted mobility-degradation factor is an order of magnitude larger than those of other planar MOSFETs. This result suggests that, while the all-around gate can turn off the electron channel effectively, it creates more interface scattering in the strong inversion condition. The extracted series resistance is mostly due to the crowding of the electron flow along the sidewall of the n+ contact region making an abrupt joint with the nanowire.
[Show abstract][Hide abstract] ABSTRACT: We report metal-free synthesis of high-density single-crystal elementary semiconductor nanowires with tunable electrical conductivities and systematic diameter control with narrow size distributions. Single-crystal silicon and germanium nanowires were synthesized by nucleation on nanocrystalline seeds and subsequent one-dimensional anisotropic growth without using external catalyst. Systematic control of the diameters with tight distribution and tunable doping concentration were realized by adjusting the growth conditions, such as growth temperature and ratio of precursor partial pressures. We also demonstrated both n-type and ambipolar field effect transistors using our undoped and phosphorus-doped metal-free silicon nanowires, respectively. This growth approach offers a method to eliminate potential metal catalyst contamination and thus could serve as an important point for further developing nanowire nanoelectronic devices for applications.
[Show abstract][Hide abstract] ABSTRACT: We reported the fabrication and characterization of a new type of silicon-on-insulator (SOI) single-electron transistor utilizing usual CMOS sidewall gate structures. We used oxide sidewall spacer layers as well as two poly-Si finger gates on an SOI wire mesa as implantation masks, to form tunnel barriers and thus a quantum dot (QD) that is smaller than the spacing between polygates. Characterization results exhibited clear Coulomb oscillations persisting up to 30 K. The Coulomb energy and the size of the QD extracted from three devices were consistent with the spacing between two poly-Si gates of each device. Furthermore, the junction capacitance of each device was almost constant and only the gate capacitance varied. These analyses suggested that the size of the QD was fully controlled by the process.
[Show abstract][Hide abstract] ABSTRACT: Recently, having vertically stacked arrays of 3D channels, multi-bridge-channel MOSFETs (MBCFETs) have been fabricated successfully (Lee et al., 2003). In this paper, we report temperature dependent transport characteristics of the MBCFET.
Semiconductor Device Research Symposium, 2007 International; 01/2008
[Show abstract][Hide abstract] ABSTRACT: The characteristics of cylindrical gate-all-around twin silicon nanowire field-effect transistors with a radius of 5 nm have been measured in temperatures T ranging from 4 to 300 K. The dependence of the off-current suggests that thermal generation in the channel is the main leakage mechanism. The dependence of the subthreshold swing exhibits no body effects but shows degradations due to slight differences in the threshold voltages and in the body effect constants of the twin nanowires. The T dependence of the peak normalized transconductance g<sub>m</sub> /V<sub>DS</sub> gives a clue of 1-D phonon scattering and suggests that surface roughness scattering at the nanowire wall is dominant at low values.
[Show abstract][Hide abstract] ABSTRACT: We report magneto-transport through a silicon-on-insulator nanowire transistor. The transport data showed Coulomb oscillations at low temperatures and a transition between positive and nega-tive magneto-conductance. At magnetic field (B) larger than the transition, the current decreases exponentially with an increase of B. Such B-dependence of the conductance, together with the observed Coulomb oscillations, is consistent with the interpretation that our nanowire transistor has a 1D-0D transport path originating from random potential fluctuations.