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ABSTRACT: InAs-AlSb high-electron mobility transistors stressed with hot carriers may exhibit shifts in the peak transconductance toward more negative gate-voltages. The devices are most degradation prone in operating conditions with high longitudinal (in the direction of IDS ) electric fields in the channel. Room-temperature annealing, gate current, and channel-mobility measurements suggest the presence of a metastable defect in the top AlSb layer. Device simulations and first-principles quantum-mechanical calculations are used to investigate the physical nature of the defects responsible for degradation. Metastable configurations of substitutional and interstitial oxygen have charge states and transition energies consistent with the degradation trends.
IEEE Transactions on Electron Devices 06/2011; · 2.32 Impact Factor
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ABSTRACT: We investigate the dependence of the single-event response of AlSb/InAs HEMTs on details of the doping, layer thicknesses, and contamination levels. The transconductance depends on the Δ-doping and layer thickness, which are shown to have the maximum impact on charge collection when the device is biased near the pinch-off voltage. In the on condition (near zero gate bias), the effect is minimal. The possible role of carbon contamination near the substrate-buffer heterointerface in reducing some of the longer transients is discussed.
IEEE Transactions on Nuclear Science 01/2011; · 1.45 Impact Factor
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ABSTRACT: Recent observations of electrical stress-induced recoverable degradation in InAs/AlSb high-electron mobility transistors (HEMTs) have been attributed to metastable defects in the AlSb layer generated by the injected holes. Here we present a detailed theoretical analysis of the degradation mechanism. We show that recoverable degradation does not require the presence of hot carriers in the vicinity of the defects but the degradation is enhanced when the injected holes become more energetic. The metastable degradation arises without the presence of an energy barrier. A comprehensive survey of candidate defects suggest that substitutional and interstitial oxygen are responsible for the degradation. Therefore, reducing the oxygen contamination during device fabrication is likely to significantly improve the reliability of InAs/AlSb HEMTs.
Journal of Applied Physics 12/2010; 108(11):114505-114505-7. · 2.17 Impact Factor
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ABSTRACT: Single event charge collection in AlSb/InAs HEMTs is shown to depend on the gate bias. Spatial correlation between excess channel carriers and the horizontal field is shown to be the key factor. Hole accumulation in the AlSb buffer layer increases the electron concentration in the two-dimensional electron gas, increasing the collected charge. Potential drop across access regions reduces charge collection towards zero gate bias. A secondary but perceptible dependence on high field electron mobility is demonstrated.
IEEE Transactions on Nuclear Science 09/2010; · 1.45 Impact Factor
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ABSTRACT: InAs-AlSb HEMTs stressed with hot electrons may exhibit shifts in the peak transconductance towards more negative gate voltages. The devices are most degradation prone in operating conditions with high vertical gate field. Annealing trends and theoretical calculations indicate the possible role of an oxygen-induced metastable defect.
Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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ABSTRACT: Single event charge collection in AlSb/InAs HEMTs is shown to depend on the gate bias. Spatial correlation between excess channel carriers and the horizontal field is shown to be the key factor. Hole accumulation in the AlSb buffer layer increases the electron concentration in the two-dimensional electron gas, increasing the collected charge.
Radiation and Its Effects on Components and Systems (RADECS), 2009 European Conference on; 10/2009
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ABSTRACT: 3-D TCAD simulation results predict reduction in single event charge collection, transient pulse widths, and charge sharing in a 90 nm bulk twin well process CMOS by using a contacted n<sup>+</sup> buried layer.
IEEE Transactions on Nuclear Science 09/2009; · 1.45 Impact Factor
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ABSTRACT: Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact layout for SET RHBD in combinational logic.
IEEE Transactions on Nuclear Science 01/2008; · 1.45 Impact Factor
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ABSTRACT: Heavy-ion testing of a radiation-hardened-by-design (RHBD) 90 nm dual interlocked cell (DICE latch) shows significant directional sensitivity results impacting observed cross-section and LET thresholds. 3-D TCAD simulations show this directional effect is due to charge sharing and parasitic bipolar effects due to n-well potential collapse.
IEEE Transactions on Nuclear Science 01/2008; · 1.45 Impact Factor
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ABSTRACT: Simulations are used to characterize the single event transient current and voltage waveforms in deep submicron CMOS integrated circuits. Results indicate that the mechanism controlling the height and duration of the observed current plateau is the redistribution of the electrostatic potential in the substrate following a particle strike. Quantitative circuit and technology factors influencing the mechanism include restoring current, device sizing, and well and substrate doping.
IEEE Transactions on Nuclear Science 01/2008; · 1.45 Impact Factor
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ABSTRACT: Three-dimensional TCAD models are used in mixed- mode simulations to analyze the effectiveness of well contacts at mitigating parasitic PNP bipolar conduction due to a direct hit ion strike. 130 nm and 90 nm technology are simulated. Results show careful well contact design can improve mitigation. However, well contact effectiveness is seen to decrease from the 130 nm to the 90 nm simulations.
IEEE Transactions on Nuclear Science 09/2007; · 1.45 Impact Factor
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ABSTRACT: Analyses of ion-induced charge sharing effects at the 90 nm CMOS technology node are discussed. Two mechanisms leading to enhanced charge collection and increased soft error sensitivity are presented.
Integrated Circuit Design and Technology, 2007. ICICDT '07. IEEE International Conference on;
