[Show abstract][Hide abstract] ABSTRACT: A high IIP2 direct-conversion receiver for cellular CDMA/PCS/GPS has been developed in a 0.35 mum SiGe BiCMOS process. This receiver consists of a RF front-end chip and a base-band chip. The RF front-end chip includes three LNAs, three mixer cores with a common output stage, and LO distribution blocks. The base-band chip includes a channel selection filter, an output buffer, and a DC calibration block. To achieve high IIP2 performance, an even-harmonic reduction technique is proposed based on a simplified analysis of second-order intermodulation. A 40-dB improvement of the IIP2 performance is accomplished by this technique, which reduces sensitivity to operating conditions and to output load mismatches. This receiver also attains high IIP3 and a low-noise figure. Measurement results show 71 dBm IIP2, -1.3 dBm IIP3, and 2.4 dB NF for Cellular CDMA; 68 dBm IIP2, - 3.7 dBm IIP3, and 2.9 dB NF for PCS; and 26 dBm IIP2 -30 dBm IIP3, and 2 dB NF for GPS.
Circuits and Systems I: Regular Papers, IEEE Transactions on 01/2008; 55-I:2934-2943. · 2.24 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The fully-monolithic diversity 2.6GHz S-DMB tuner IC features a NF of <1.8dB, a path isolation of over 25dB, a DR of over 100dB with <4dB path gain mismatch and a power consumption of 112mW. This IC is implemented in a 0.25 mum SiGe BiCMOS process. The chip is verified in S-DMB systems using several commercially available S-DMB demodulator chips
[Show abstract][Hide abstract] ABSTRACT: The paper presents a fully integrated low power direct conversion transmitter IC for CDMA applications. To reduce the power consumption and reduce switching time, a fractional-N frequency synthesizer with an internal VCO is integrated into the transmitter IC and an N-target algorithm is proposed to implement automatic frequency calibration (AFC). Total locking time is approximately 200 μs, including 80 μs AFC lock time. Total current consumption for -80 dBm, -10 dBm, and 8 dBm output power are 27 mA, 33 mA, and 60 mA, respectively. This chip is housed in a small 5 mm × 5 mm 32 pin MLF package.
Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE; 07/2005
[Show abstract][Hide abstract] ABSTRACT: An even-harmonic reduction technique to enhance IIP2 (second order input intercept point) performance in a direct-conversion mixer is proposed based on a simplified analysis of second-order intermodulation. Using the proposed technique, IIP2 performance can be improved while reducing sensitivity to operating condition and output load mismatch. Direct-conversion mixers for cellular CDMA, PCS, and GPS applications are designed and fabricated in a 0.35 μm SiGe BiCMOS process. Measurement results show 40 dB improvement and reduced sensitivity of IIP2, which are consistent with simulation results.
Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE; 07/2004
[Show abstract][Hide abstract] ABSTRACT: A fully temperature-compensated linear-in-dB variable gain amplifier (VGA) is presented. The VGA achieves wide dynamic range and precise linear-in-dB control capability using a translinear current amplifier. The compensation technique having current proportional to the squared temperature is proposed. The VGA is implemented with 0.35 μm SiGe BiCMOS process. Greater than 90 dB dynamic range while having only ±3 dB gain drift from -30°C to 85°C temperature range is measured.
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on; 06/2003