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ABSTRACT: In this paper, a tailbiting block-interleaved pipelining (BIP) architecture is proposed for high-throughput and energy efficient WiMAX turbo decoders. Conventional sliding window (SW) BIP turbo decoders suffer from many warm-up calculations and large memory size when the number of pipeline stages is increased. Instead of the SW, we combined the tailbiting method with BIP. Consequently, more than 50% of the warm-up calculation was reduced, and necessary memory size became constant. We have implemented a tailbiting BIP WiMAX turbo decoder with 4 pipeline stages in the area of 3.8 mm<sup>2</sup> using a 0.18 ¿m CMOS technology. The chip achieves 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian; 12/2009
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ABSTRACT: A high-efficiency CMOS rectifier circuit for UHF RFIDs was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. A differential-drive active gate bias mechanism simultaneously enables both low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large power conversion efficiency (PCE), especially under small RF input power conditions. A test circuit of the proposed differential-drive rectifier was fabricated with 0.18 mu m CMOS technology, and the measured performance was compared with those of other types of rectifiers. Dependence of the PCE on the input RF signal frequency, output loading conditions and transistor sizing was also evaluated. At the single-stage configuration, 67.5% of PCE was achieved under conditions of 953 MHz, - 12.5 dBm RF input and 10 KOmega output load. This is twice as large as that of the state-of-the-art rectifier circuit. The peak PCE increases with a decrease in operation frequency and with an increase in output load resistance. In addition, experimental results show the existence of an optimum transistor size in accordance with the output loading conditions. The multi-stage configuration for larger output DC voltage is also presented.
IEEE Journal of Solid-State Circuits 12/2009; · 3.23 Impact Factor
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ABSTRACT: Two types of CMOS rectifier circuits for UHF RFIDs have been proposed. Large power conversion efficiency (PCE) has been achieved by Vth cancellation techniques. In the Self-Vth-Cancellation (SVC) CMOS rectifier, the threshold voltage of MOSFETs is cancelled by gate bias voltage generated from the output voltage of the rectifier itself, resulting in excellent PCE. The differential-drive CMOS rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. A differential-drive scheme realizes an active gate bias mechanism and simultaneously enables both low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large PCE, especially under small RF input power conditions. Test circuits for both types of rectifiers were fabricated and the measured performances were compared with those of conventional rectifiers.
ASIC, 2009. ASICON '09. IEEE 8th International Conference on; 11/2009
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ABSTRACT: A high efficiency differential CMOS rectifier circuit for UHF RFIDs was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. Differential-drive topology enables simultaneous low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large power conversion efficiency(PCE), especially under small RF input power conditions. The differential-drive rectifier was fabricated with 0.18-mum CMOS technology, and the measured performance was compared with those of other types of rectifiers. Dependence of the PCE on an input RF signal frequency and output loading conditions was also evaluated. 66% of PCE was achieved under conditions of 953 MHz, -12 dBm RF input and 10 KOmega DC output load. This is twice as large as that of the state-of-the-art rectifier circuit. The peak PCE increases with a decrease in operation frequency and with an increase in output load resistance.
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian; 12/2008
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ABSTRACT: High efficiency CMOS rectifier circuit for UHF RFID applications has been developed. The rectifier utilizes self Vth cancellation (SVC) scheme in which threshold voltage of MOSFETs is cancelled by applying gate bias voltage generated by output voltage of the rectifier itself. Very simple circuit configuration and no power dissipation feature of the scheme enable excellent power conversion efficiency (PCE) especially in small RF input power conditions. At higher RF input power conditions, PCE of the rectifier automatically decreases. This is the built-in self-power-regulation function. Proposed SVC CMOS rectifier has been fabricated with 0.35 mum CMOS process and the measured performance has been compared with other types of rectifiers. The SVC CMOS rectifier achieves 29% PCE at -9.9 dBm RF input power condition. This PCE is larger than ever reported rectifiers under the condition.
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian; 12/2007
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ABSTRACT: Vector quantization (VQ) is a popular signal compression method. In a VQ framework, the encoding speed is one of the key issues for its practical applications. In principle, the high dimension of the original (nxn)-dimensional vectors is the reason that makes it is computationally very expensive to find the best-matched codeword for a given input vector by computing Euclidean distances. As a result, a lot of fast VQ encoding methods have been developed in the previous works based on using scalar statistical features (i.e., sum, variance or L<sub>2</sub> norm) or lower dimensional multi-resolution representation (i.e., various pyramid data structures) of a vector to deal with this computational complexity problem caused by the high dimension of the original vectors, hi particular, a very effective mixed-pyramid data structure is reported in the previous work [7], which features a minimum configuration by combining a 2-PM core sum pyramid and a (nxn)-PM auxiliary variance pyramid together. However, this mixed-pyramid failed to take the element order of a vector into account. hi order to further improve the encoding performance of the previous work [7], this paper proposes to introduce a dynamic element reordering operation to let all elements of a codeword rearranged in an ascending order by an offline sorting process before it goes to construct the mixed-pyramid for the codeword. After the element reordering, it is possible to make the intermediate levels in the mixed-pyramid of a codeword keep more energy and become more powerful for rejection tests. Experimental results confirmed that the encoding efficiency of the proposed method remarkably outperforms the previous work [7].
Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on; 09/2007
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ABSTRACT: The encoding process of vector quantization (VQ) is very expensive computationally. By using the statistical features of the sum and the variance of a k-D whole vector, IEENNS method has been proposed to reject unlikely codewords. To further enhance the performance of IEENNS method, by first partitioning a k-D whole vector in half to generate its two (k/2)-D fixed subvectors and then directly applying IEENNS method once again to each sub vector, a complete- version C-SIEENNS method and a simplified-version S- SIEENNS method have been proposed. By offline sorting the elements of a codeword before subvector partition, an adaptive A-SIEENNS method has been reported recently as well. However, there is no guarantee that these subvector partition methods are optimal. Thus, this paper proposes a practical criterion to optimally partition a k-D whole vector into a k<sub>2</sub>-D first subvector and a k2-D second subvector (k<sub>1</sub>+k<sub>2</sub>=k) by maximizing the energy included in the two partial sums of a codeword. Experimental results confirmed that this work can improve search efficiency significantly compared to the latest A-STEENNS method.
Digital Signal Processing, 2007 15th International Conference on; 08/2007
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ABSTRACT: In a vector quantization (VQ) framework, one of the key problems in its practical applications is the encoding speed. In order to speed up VQ encoding process, it is most important to avoid computing unnecessary k-dimensional (k-D) real Euclidean distances for the obviously unlikely candidate codewords. The mean, the variance and the two partial sums of a k-D vector have already been proposed as the effective features in the previous works in order to realize a rejection to the unlikely codeword by using just a little computational cost. It is clear that the mean and the variance of a k-D vector are constant but the two partial sums of a k-D vector are not constant depending on how they have been constructed. Therefore, how to construct two better partial sums for fast VQ encoding becomes important. Instead of using fixed the first half vector and the second half vector criterion that has been introduced in the previous works, this paper proposes a new energy-maximum criterion to construct two better partial sums for a k-D vector. Mathematical analysis and experimental results confirmed that the proposed criterion is much more effective for fast VQ encoding compared to the fixed criterion used in the previous works. In addition, it is very easy to use the energy-maximum criterion in practice
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on; 01/2007
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ABSTRACT: To implement a user circuit on a Dynamically Reconflgurable FPGA (DRFPGA) the circuit needs to be temporally partitioned into several sub-circuits such that their sequential execution on the DRFPGA yields the same result as that of the user circuit. In devices where interconnect delay is far dominating than logic delay, such implementation has the prospect of executing user circuits faster than traditional FPGA implementation, since temporal partitioning divides a long spatial wire of a circuit into several short temporal wires, thus converting interconnect delay into logic delay. To realize such prospect, reconfiguration delay and temporal communication delay of a DRFPGA must be kept as low as possible. This paper studies these issues and reports the architecture and performance of Flexible Processor III (FP3), a newly proposed DRFPGA. FP3 employs a new shift register type temporal interconnect and Nearest Neighbor (NN) type spatial interconnect to reduce the delay mentioned above. Correct behavior of FP3, designed and fabricated in 0.35 um CMOS technology, has been confirmed and our experimental results show that there exist cases where the best user circuit speed is achieved when two or more contexts are in use.
Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian; 12/2006
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ABSTRACT: Vector quantization (VQ) is a popular image compression method and the encoding speed of VQ is very important to its practical applications. In a conventional encoding process of VQ, because a lot of k-dimensional (k-D) Euclidean distances must be computed so as to find out the best-match for each input vector, VQ is computationally very expensive. In order to avoid immediately computing the real Euclidean distance for a candidate codeword, IEENNS method has been proposed to reject the unlikely codeword by using the famous scalar features of the sum and the variance of a k-D vector. Furthermore, in order to improve the precision of Euclidean distance estimation so as to enhance the rejection capability, by dividing a k-D vector in half to generate two (k/2)-D subvectors and then apply IEENNS method again to each of the subvectors, a complete-version C-SIEENNS method and a simplified-version S-SIEENNS method have been reported recently as well. Apparently, how to construct the two (k/2)-D subvectors is the core problem in a subvector-based method for achieving a higher encoding performance. However, the previous works just fixedly construct their two subvectors by using the first half original vector of [1 ~ k/2] dimensions and the second half original vector of [k/2+1 ~ k] dimensions for simplicity. It is clear there is no guarantee that this kind of subvector construction way is optimal. Instead, this paper proposes a criterion to construct two better subvectors by letting the difference between the two partial sums approach the maximum based on adaptively analyzing the property of each codeword offline. Experimental results confirmed that by simply replacing the fixed subvectors with the adaptively constructed subvectors in S-SIEENNS method, it can further improve the search efficiency by 19.9% ~ 36.8%
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on; 06/2006
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ABSTRACT: This paper reports that the low-frequency noise in p-channel MOSFETs fabricated on [110] and (100) crystallographic oriented silicon is related to the microroughness of the silicon surface. Since the conventional RCA cleaning process makes the surface rough, especially in the case of [110] orientation, the authors developed the so-called 5-step room temperature cleaning process that does not use alkaline solution. The combination of this new cleaning process with the microwave-excited high-density plasma oxidation process for the formation of the gate oxide, instead of the standard 900°C thermal oxidation process, leads to a reduction of the microroughness and a drop in the 1/f noise level of more than one decade. Furthermore, this reduction is not only observed for the [110] orientation but also seen, albeit to a much lesser extent, for (100) if it is treated in the same way.
IEEE Transactions on Electron Devices 05/2006; · 2.32 Impact Factor
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ABSTRACT: In a framework of vector quantization (VQ), the encoding speed is a key issue for its practical applications. To speed up the VQ encoding process, Walsh transform is introduced in the previous work to map vectors in a k-dimensional (k-D) spatial domain into k-D Walsh domain in order to exploit the energy-compaction property of an orthogonal transform. However, there still exist a serious problem in that previous work because it just simply used the most common sequency-ordered Walsh transform kernel, which is actually not very high efficient for fast VQ encoding. In order to solve the kernel order problem in VQ encoding this paper proposes an optimal order for Walsh transform kernel based on the energy distribution of a particular codebook at each dimension in a k-D Walsh domain, which requires that the dimension with a larger energy distribution be put forward to be as a lower dimension. Experimental results confirmed that the proposed method could reduce the computational cost to 85.9% ∼ 53.1% compared to the previous work so as to enhance its performance obviously.
Image Processing, 2005. ICIP 2005. IEEE International Conference on; 10/2005
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ABSTRACT: The L<sub>2</sub>-norm pyramid has already been investigated as a promising data structure for the fast search of vector quantization (VQ) encoding in the previous work. Because the distortion at the top level is always tested first when using such a conventional L<sub>2</sub>-norm pyramid, the top level is most important. In order to enhance the capability of achieving a rejection decision at the top level, a modification is introduced into the conventional L<sub>2</sub>-norm pyramid in this letter by using both the mean and the variance of a vector simultaneously to replace the L<sub>2</sub>-norm of the vector for distortion computation at the top level. Two issues are made clear as 1) why this modification is beneficial to the distortion test is proved and 2) why only the top level of a conventional L<sub>2</sub>-norm pyramid should be modified is interpreted as well. Experimental results confirmed that the performance of VQ encoding by using the modified L<sub>2</sub>-norm pyramid can be improved obviously.
IEEE Signal Processing Letters 10/2005; · 1.39 Impact Factor
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ABSTRACT: The encoding speed of vector quantization (VQ) is an important problem for VQ's practical applications. Because a k-dimensional (k-D) vector can also be mathematically viewed as a k-element set so that the statistical analysis methods can be directly applied to k-D vectors. In order to approximately measure the difference between two k-D vectors, by using the well-known statistical features of the sum and the variance of a k-D vector first, the IEENNS method (S. Baek, et al., IEEE Signal Processing Letters, vol.4, pp.325-327, 1997) has been proposed to reject most of unlikely codewords for a certain input vector. Then, by dividing a k-D vector in half to generate its two corresponding (k/2)-D subvectors and then apply the IEENNS method again to each of the subvectors, a complete-version SIEENNS method (J.S. Pan, et al., IEEE Trans. Image Processing, voL12. pp.265-270, 2003) has been proposed as well. Because the SIEENNS method still has a large memory and computational redundancy, a simplified-version enhanced ESIEENNS method (Z. Pan et al., 2005 International Symposium on Circuits and Systems, pp.6332-6335, 2005) is reported recently. However, all of these subvector-based previous works just fixedly constructed its two subvectors for simplicity, which cannot guarantee a very high search performance. Instead, this paper proposes to dynamically construct the two subvectors more efficiently based on a criterion of |S<sub>y,j</sub> - S<sub>y,j</sub>| ⇒ max by offline analyzing the property of a codeword y<sub>i</sub>. Experimental results confirmed that the proposed DESIEENNS method can improve the total search efficiency to 79.9% ∼ 88.7% compared to the latest ESIEENNS method for various input images.
Circuits and Systems, 2005. 48th Midwest Symposium on; 09/2005
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ABSTRACT: The encoding process of image vector quantization (VQ) is very heavy due to it performing a lot of k-dimensional Euclidean distance computations. In order to speed up VQ encoding, it is most important to avoid unnecessary exact Euclidean distance computations as many as possible by using features of a vector to estimate how large it is first so as to reject most of unlikely codewords. The mean, the variance, L <sub>2</sub> norm and partial sum of a vector have been proposed as effective features in previous works for fast VQ encoding. Recently, in the previous work (Z. Lu et al., 2003), three features of the mean, the variance and L<sub>2</sub> norm are used together to derive an EEENNS search method, which is very search efficient but still has obvious computational redundancy. This paper aims at modifying the results of EEENNS method further by introducing another feature of partial sum to replace L<sub>2</sub> norm feature so as to reduce more search space. Mathematical analysis and experimental results confirmed that the proposed method is more search efficient compared to (Z. Lu et al., 2003)
Multimedia and Expo, 2005. ICME 2005. IEEE International Conference on; 08/2005
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ABSTRACT: The encoding speed of vector quantization (VQ) is a time bottleneck to its practical applications due to it performing a lot of k-dimensional (kD) Euclidean distance computations. By using famous statistical features of the sum and the variance of a kD vector to estimate the Euclidean distance first, an IEENNS (improved equal-average equal-variance nearest neighbor search) method has been proposed to reject most of the unlikely codewords for a certain input vector. By dividing a kD vector in half to generate its two corresponding (k/2)D subvectors and then apply the IEENNS method again to each subvector, an SIEENNS (subvector-based IEENNS) method has been proposed as well. The SIEENNS method is, so far, the most search-efficient subvector-based encoding method for VQ, but it still has a large memory and computational redundancy. The paper aims at improving the state-of-the-art SIEENNS method by introducing a new 3-level data structure to reduce memory redundancy and by avoiding using the variances of two (k/2)D subvectors to reduce computational redundancy. Experimental results confirmed that the proposed method can reduce memory requirement for each kD vector from (k+6) to (k+1) and, at the same time, improve total search efficiency by 20-30% compared to the SIEENNS method.
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on; 06/2005
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Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on; 02/2005
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ABSTRACT: This work introduces a new approach to realize timesharing of flip-flops in time-multiplexed FPGAs. In order to implement large circuits in time-multiplexed FPGAs, it is important that flip-flops, as well as combinational logics, must be time-shared efficiently. To handle sequential circuits, previous works either required large amount of communication between sub-circuits or caused storage overhead due to buffer usage, resulting to complicated placing and routing tasks and limiting the size of target circuit that can be implemented. We propose a simple algorithm that can efficiently realize timesharing of flip-flops by refining an initial partitioning. Experimental results show that implementation of our approach can eliminate all storage overhead while the resultant change in the amount of communication between sub-circuits can be kept less than ±4%. We have also designed and fabricated a new temporal communication module, and implemented our new approach on it.
Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on; 01/2005
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ABSTRACT: The encoding process of vector quantization (VQ) is a time bottleneck to its practical application. In order to speed up the process of VQ encoding, it is possible to estimate the Euclidean distance first with just a lighter computation to try to reject a candidate codeword. In order to estimate the Euclidean distance, appropriate features of a vector become necessary. By using the famous statistical features of the sum and variance for a k-dimensional vector and furthermore for its two corresponding (k/2)-dimensional subvectors, it is easy to estimate the Euclidean distance so as to reject most of the unlikely codewords for a certain input vector (Guan, L and Kamel, M., 1992; Lec, C.H. and Chen, L H., 1994; Baek, S. et al., 1997; Pan, J.S. et al., 2003). Because it is very heavy to compute the variance of a k-dimensional vector online, a new feature, which is based on the variances of two subvectors, is constructed to estimate the Euclidean distance. Meanwhile, a modified more memory-efficient data structure is proposed for storing all features of a vector to reduce extra memory requirement compared to the latest previous work (Pan, J.S. et al., 2003). Experimental results confirmed that the proposed method is more search efficient.
Intelligent Signal Processing and Communication Systems, 2004. ISPACS 2004. Proceedings of 2004 International Symposium on; 12/2004
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ABSTRACT: In a framework of vector quantization (VQ), the fast search method for finding the best-matched codeword (winner) is a key issue because it is the time bottleneck for practical applications. To speed up VQ encoding process, some fast search methods that are based on the concept of projection axes or Walsh transform have already been proposed in previous works (L. Guan and M. Kamel, Oct 1992)-(S. Baek and K. Sung 2001). However, there still exist two serious problems in them because they use both spatial domain and partial Walsh domain simultaneously. First, they need extra memories for storing projected values on selected projection axes or the first several elements in partial Walsh domain, which becomes an overhead of memory. Second, once all rejection tests fail finally, they completely discard the obtained distortion that has already been computed in partial Walsh domain and return to spatial domain to compute real Euclidean distance again from the very beginning, which is certainly a waste and becomes an overhead of computation. In order to solve the overhead problems of both memory and computation as described above, firstly a memory-efficient storing way for a vector is proposed by completely mapping a vector into Walsh domain but NOT using-the original spatial domain any more, which can avoid extra memory requirement Secondly, the discarded distortion in partial Walsh domain is reused so as to avoid any waste to the executed computation. In addition, a more efficient rejection test is suggested to reduce more search space. Experimental results confirmed that the proposed method outperforms the previous works obviously.
Image Processing, 2004. ICIP '04. 2004 International Conference on; 11/2004
