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2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011; 01/2011
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Proceedings of the 16th Asia South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, January 25-27, 2011; 01/2011
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ABSTRACT: Deep submicron processes have allowed field-programmable gate arrays (FPGAs) to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process variation. In order to obtain sufficient yield values, it is now necessary to consider process variation during physical design. It is common for FPGAs to contain designs with multi-cycle paths to help increase the performance, but current statistical static timing analysis (SSTA) techniques cannot support this type of timing constraint. In this paper, we propose an extension to block-based SSTA to consider multi-cycle paths. We then use this new SSTA to optimize FPGA placement with our tool VMC-Place for designs with multi-cycle paths. Experimental results show our multi-cycle SSTA is accurate to 0.59% for the mean and 0.0024% for the standard deviation. Our results also show that VMC-Place is able to reduce the 95% performance yield clock period by 15.36% as compared to VPR.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12/2010; · 1.27 Impact Factor
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ABSTRACT: This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. This paper also presents an enhanced clustering algorithm that considers dual supply voltages, honoring the dual-Vdd mapping solution. To carry out various comparisons, we first design a single-Vdd mapping algorithm, named SVmap-2, which achieves a 3.8% total power reduction (15.6% dynamic power reduction) over a previously published low-power mapping algorithm, Emap . We then show that our dual-Vdd mapping algorithm, named DVmap-2, can further improve total power savings by 12.8% over SVmap-2, with a 52.7% dynamic power reduction. Compared to the early single-Vdd version SVmap , DVmap-2 is 14.3% better for total power reduction. This is achieved through an ideal selection of the low-Vdd/high-Vdd ratio and the consideration of various voltage changing scenarios during the mapping process.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12/2010; · 1.27 Impact Factor
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IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2010; 29:1818-1822.
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IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2010; 29:1709-1722.
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Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010; 01/2010
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Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009; 01/2009
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ABSTRACT: In the hunt to find a replacement to CMOS, material scientists are devel-oping a wide range of nanomaterials and nanomaterial-based devices that offer signif-icant performance improvements. One example is the Carbon Nanotube Field Effect Transistor, or CNFET, which replaces the traditional silicon channel with an array of semiconducting carbon nanotubes (CNTs). Given the increased variation and defects of nanometer-scale fabrication, and the regular nature of bottom-up self-assembly, field programmable devices are a promising initial application for such technolo-gies. In this paper, we detail the design and evaluation of a novel nanomaterial-based architecture called FPCNA (Field Programmable Carbon Nanotube Array). New nano-material-based circuit building blocks are developed and characterized, including a lookup table created entirely from continuous CNT ribbons. To accurately determine the performance of these building blocks, we create variation-aware physical design tools with statistical timing analysis that can handle both Gaussian and non-Gaussian random variables. When the FPCNA architecture is evaluated using this CAD flow, we see a 2.75× performance improvement over an equivalent CMOS FPGA at a 95% yield. In addition, FPCNA offers a 5.07× footprint reduction compared to the baseline FPGA.
Int J Parallel Prog Int J Parallel Prog. 01/2009; 37(37):389-416389.
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IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, 13-15 May 2009, Tampa, Florida, USA; 01/2009
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International Journal of Parallel Programming. 01/2009; 37:389-416.
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Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009; 01/2009
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ABSTRACT: In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA , which utilizes 3D integration techniques and new nanoscale materials synergistically. The proposed architecture is based on CMOS-nano hybrid techniques that incorporate nanomaterials such as carbon nanotube bundles and nanowire crossbars into CMOS fabrication process. Using unique features of FPGAs and a novel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4.5X footprint reduction compared to traditional CMOS-based 2D FPGAs. With a customized design automation flow, we evaluate the performance and power of 3D nFPGA driven by the 20 largest MCNC benchmarks. Results demonstrate that 3D nFPGA is able to provide a performance gain of 2.6X with a small power overhead comparing to the CMOS 2D FPGA architecture.
Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on; 12/2007
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ABSTRACT: In this paper, we introduce a novel reconfigurable architecture, named 3D field-programmable gate array (3D nFPGA), which utilizes 3D integration techniques and new nanoscale materials synergistically. The proposed architecture is based on CMOS nanohybrid techniques that incorporate nanomaterials such as carbon nanotube bundles and nanowire crossbars into CMOS fabrication process. This architecture also has built-in features for fault tolerance and heat alleviation. Using unique features of FPGAs and a novel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4x footprint reduction comparing to the traditional CMOS-based 2D FPGAs. With a customized design automation flow, we evaluate the performance and power of 3D nFPGA driven by the 20 largest MCNC benchmarks. Results demonstrate that 3D nFPGA is able to provide a performance gain of 2.6 x with a small power overhead comparing to the traditional 2D FPGA architecture.
Circuits and Systems I: Regular Papers, IEEE Transactions on 12/2007; · 1.97 Impact Factor
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International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece; 01/2006
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ABSTRACT: In this paper we propose a Fast Data Relay (FDR) mechanism and the supporting compiler techniques to enhance existing CGRA. Our results on FDR-based CGRA are compared with two other works in this field: ADRES and RCP. Experimental results for various multimedia applications show that FDR combined with a routing based resource conflict solver enables us to deliver up to 29% and 21% higher performance than ADRES and RCP, respectively.
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ABSTRACT: The electrical properties of metallic carbon nanotubes (CNT) can rival, or even exceed, the best metals known. It is a potential candidate for future on-chip interconnect, whose performance will be dominant in the next generation integrated circuits. In this paper, a study on the modeling and simulation techniques for the CNT interconnect network is carried out. The frequency-independent models of CNT interconnects in terms of resistance, inductance and capacitance are summarized. A novel frequency-dependent circuit model is proposed for CNT for various high-frequency applications. Preliminary analysis shows a good match between numerical simulations and the compact model. The proposed modeling and simulation techniques for CNT interconnect network are expected to play an important role in the future CNT nanotechnology applications. Introduction Carbon nanotubes (CNTs) were discovered in 1991 by Sumio Iijima while working at NEC Research Laboratories in Tsukuba, Japan [1]. Since the discovery of carbon nanotubes, there has been intense activity exploring the electrical properties of these systems and their potential applications in electronics [2, 3]. Experiments and theories have shown that the electrical properties of carbon nanotubes can rival, or even exceed, the best metals and semiconductors known. Thus, the carbon nanotube-based electrical circuits are very promising for the next-generation of VLSI industry [2-5]. There exist two kinds of carbon nanotubes. Multiwall nanotubes (MWCNTs) are more common and are rolled-up stacks of graphene sheets in concentric carbon nanotubes. A single-wall carbon nanotube (SWCNT) is a rolled-up shell of graphene sheet made of benzene-type hexagonal carbon rings. SWCNT technology shows significant promise in acting as both transistors and interconnects in future generations of VLSI circuits. Compared with the conventional metal interconnections, SWCNTs can sustain a high current density without electro-migration problem. In this manner, it shows a great potential for electronic applications. In addition, the SWCNTs also overcome the high-resistance problem, often existing when the conventional metal interconnections are scaled down [3, 4]. The RLC circuit model of SWCNTs has been recently established and the equations of parameters in the circuit model have been given [5]. Yet, so far, most of the equations are frequency-independent. In various high-frequency applications, the frequency-dependent impedance models are much useful. The goal of this paper is to express the RLC parameters as a function of frequency based on existing circuit model and the experimental results [3, 4]. Therefore, new frequency-dependent models for R, L, C of SWCNT interconnects are derived for high-frequency applications. Based on these new models, simulation results are obtained and compared with the experimental results. Frequency-independent Circuit Model for SWCNT SWCNT technologies are very promising for the future of VLSI circuit, and interconnect design. As shown in Fig. 1, the frequency-independent model in terms of R, L, C has recently been derived for SWCNT interconnects [3, 4].
