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ABSTRACT: Emerging applications such as flash-based storage systems and 10 gigabit Ethernet require that there is no error floor even at bit error rates as low as 10<sup>-12</sup> or so. It has been found that trapping sets are responsible for the error floors of many LDPC codes with AWGN channels. This paper presents a hardware based backtracking scheme to break the trapping sets at runtime for lowering the error floor of quasi-cyclic LDPC codes. Backtracking is implemented as a self-contained module that can be interfaced to any generic reconfigurable iterative decoder for QC-LDPC codes. The backtracking module and a reconfigurable decoder are implemented with a FPGA and an 180 nm standard cell library. The results indicate that the overhead of backtracking is modest - about 5% in terms of logic and 13% in terms of memory for the first level backtracking and 14% in terms of logic and 46% in terms of memory for a two-level backtracking scheme. Furthermore, it is shown that the increase in latency due to backtracking is modest in the average case and can be controlled by the system designer by choosing the appropriate values for the number of trials and the number of iterations of the backtracking module.
Circuits and Systems I: Regular Papers, IEEE Transactions on 01/2012; · 1.97 Impact Factor
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ABSTRACT: Error-floors are the main reason for excluding LDPC codes from applications requiring very low bit-error rate. They are attributed to a particular structure in the codes' Tanner graphs, known as trapping sets, which traps the message-passing algorithms commonly used to decode LDPC codes, and prevents decoding from converging to the correct codeword. A technique is proposed to break trapping sets while decoding. Based on decoding results leading to a decoding failure, some bits are identified in a previous iteration and flipped and decoding is restarted. This backtracking may enable the decoder to get out of the trapped state. A semi-analytical method is also proposed to predict the error-floor after backtracking. Simulation results indicate the effectiveness of the proposed technique in lowering the error-floor. The technique, which has moderate complexity overhead, is applicable to any code without requiring a prior knowledge of the structure of its trapping sets.
IEEE Transactions on Communications 02/2011; · 1.68 Impact Factor
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ABSTRACT: Designers are increasingly relying on field-programmable gate array (FPGA)-based emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically down to bit-error rates of 10<sup>-12</sup> and below. This requires decoding architectures that can take advantage of the unique characteristics of a modern FPGA to maximize the decoding throughput. This paper presents two specific optimizations called vectorization and folding to take advantage of the configurable data-width and depth of embedded memory in an FPGA to improve the throughput of a decoder for quasi-cyclic LDPC codes. With folding it is shown that quasi-cyclic LDPC codes with a very large number of circulants can be implemented on FPGAs with a small number of embedded memory blocks. A synthesis tool called QCSyn is described, which takes the H matrix of a quasi-cyclic LDPC code and the resource characteristics of an FPGA and automatically synthesizes a vector or folded architecture that maximizes the decoding throughput for the code on the given FPGA by selecting the appropriate degree of folding and/or vectorization. This helps not only in reducing the design time to create a decoder but also in quickly retargeting the implementation to a different (perhaps new) FPGA or a different emulation board.
Circuits and Systems I: Regular Papers, IEEE Transactions on 02/2011; · 1.97 Impact Factor
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IEEE Trans. on Circuits and Systems. 01/2011; 58-I:98-111.
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IEEE Transactions on Communications. 01/2011; 59:64-73.
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IEEE Trans. on Circuits and Systems. 01/2011; 58-I:2931-2943.
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ABSTRACT: This paper presents two new large classes of QC-LDPC codes, one binary and one non-binary. Codes in these two classes are constructed by array dispersions of row-distance constrained matrices formed based on additive subgroups of finite fields. Experimental results show that codes constructed perform very well over the AWGN channel with iterative decoding based on belief propagation. Codes of a subclass of the class of binary codes have large minimum distances comparable to finite geometry LDPC codes and they offer effective tradeoff between error performance and decoding complexity when decoded with low-complexity reliability-based iterative decoding algorithms such as binary message passing decoding algorithms. Non-binary codes decoded with a Fast-Fourier Transform based sum-product algorithm achieve significantly large coding gains over Reed-Solomon codes of the same lengths and rates decoded with either the hard-decision Berlekamp-Massey algorithm or the algebraic soft-decision Kotter-Vardy algorithm. They have potential to replace Reed-Solomon codes in some communication or storage systems where combinations of random and bursts of errors (or erasures) occur.
IEEE Transactions on Communications 06/2010; · 1.68 Impact Factor
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IEEE Transactions on Communications. 01/2010; 58:1383-1396.
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ABSTRACT: This paper presents two novel reliability-based iterative majority-logic decoding algorithms for LDPC codes. Both algorithms are binary message-passing algorithms and require only logical operations and integer additions. Consequently, they can be implemented with simple combinational logic circuits. They either outperform or perform just as well as the existing weighted bit-flipping or other reliability-based iterative decoding algorithms for LDPC codes in error performance with a faster rate of decoding convergence and less decoding complexity. Compared to the sum-product algorithm for LDPC codes, they offer effective trade-offs between performance and decoding complexity.
IEEE Transactions on Communications 01/2010; · 1.68 Impact Factor
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ABSTRACT: This paper presents two novel iterative reliability-based majority-logic algorithms for decoding LDPC codes. Both algorithms are binary message-passing algorithms and require only logical operations and integer additions. Consequently, they can be implemented with simple combinational logic circuits. They either outperform or perform just well as the existing weighted bit-flipping or other reliability-based decoding algorithms for LDPC codes in error performance with a faster rate of decoding convergence and less decoding complexity. Compared to the sum-product algorithm for LDPC codes, they offer effective trade-offs between performance and decoding complexity.
Information Theory Workshop, 2009. ITW 2009. IEEE; 11/2009
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ABSTRACT: This paper presents a soft reliability-based binary message-passing algorithm for decoding LDPC codes. This algorithm outperforms the existing weighted bit-flipping algorithms with much less computational complexity. It is particularly effective for decoding LDPC codes constructed based on finite-geometries and finite fields. The proposed algorithm can be simplified for applications in communication or storage systems where either soft reliability information is not available to the decoder or a simple decoder is needed.
Communication, Control, and Computing, 2009. Allerton 2009. 47th Annual Allerton Conference on; 11/2009
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ABSTRACT: This paper presents two algebraic methods for constructing high performance and efficiently encodable nonbinary quasi-cyclic LDPC codes based on arrays of special circulant permutation matrices and multi-fold array dispersions. Codes constructed based on these methods perform well over the AWGN and other types of channels with iterative decoding based on belief-propagation. Experimental results show that over the AWGN channel, these non-binary quasi-cyclic LDPC codes significantly outperform Reed-Solomon codes of the same lengths and rates decoded with either algebraic hard-decision Berlekamp-Massey algorithm or algebraic soft-decision Kotter-Vardy algorithm. Also presented in this paper is a class of asymptotically optimal LDPC codes for correcting bursts of erasures. Codes constructed also perform well over flat fading channels. Non-binary quasi-cyclic LDPC codes have a great potential to replace Reed-Solomon codes in some applications in communication environments and storage systems for combating mixed types of noises and interferences.
IEEE Transactions on Communications 07/2009; · 1.68 Impact Factor
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ABSTRACT: This paper presents algebraic methods for constructing high performance and efficiently encodable non-binary quasi-cyclic LDPC codes based on flats of finite Euclidean geometries and array masking. Codes constructed based on these methods perform very well over the AWGN channel. With iterative decoding using a fast Fourier transform based sum-product algorithm, they achieve significantly large coding gains over Reed-Solomon codes of the same lengths and rates decoded with either algebraic hard-decision Berlekamp-Massey algorithm or algebraic soft-decision Kotter-Vardy algorithm. Due to their quasi-cyclic structure, these non-binary LDPC codes on Euclidean geometries can be encoded using simple shift-registers with linear complexity. Structured non-binary LDPC codes have a great potential to replace Reed-Solomon codes for some applications in either communication or storage systems for combating mixed types of noise and interferences.
IEEE Transactions on Communications 06/2009; · 1.68 Impact Factor
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IEEE Transactions on Communications. 01/2009; 57:1298-1311.
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IEEE Transactions on Communications. 01/2009; 57:1652-1662.
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IEEE Transactions on Communications. 01/2009; 57:3597-3606.
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Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009; 01/2009
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ABSTRACT: This paper investigates error control at the physical layer of a multicast network using low-density parity-check (LDPC) codes. Packets for transmission are encoded into LDPC codewords. A joint iterative message-passing scheme for decoding LDPC codewords at a receive node in the network is proposed to improve error performance. Also proposed is a split-codeword transmission to provide equal error protection for all transmitted packets. Density evolution analysis and some simulation results are also presented.
Information Theory, 2008. ISIT 2008. IEEE International Symposium on; 08/2008
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ABSTRACT: This paper presents two new algebraic constructions of high performance non-binary quasi-cyclic LDPC codes based on array dispersions of matrices over non-binary fields. Codes constructed perform well over the AWGN channel with iterative decoding using a Fast Fourier Transform based sum-product algorithm. They achieve significantly large coding gains over Reed-Solomon codes of the same lengths and rates decoded with either the hard-decision Berlekamp-Massey algorithm or the algebraic soft-decision Koetter-Vardy algorithm. Due to their quasi-cyclic structure, they can be efficiently encoded using simple shift-registers with linear complexity. They have a potential to replace RS codes for some applications in communication and storage systems.
Information Theory, 2008. ISIT 2008. IEEE International Symposium on; 08/2008
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Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November - 4 December 2008; 01/2008
