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ABSTRACT: Using a microfluidic system based on PTFE tubes, experimental results of contactless and label-free characterization techniques of yeast cell cultivation are presented. The PTFE tube has an inner diameter of 0.5 mm resulting in a sample volume of 2 μ1 for 1 cm sample length. Two approaches (at frequencies around 7 GHz and 240 GHz) are presented and compared in terms of sensitivity and applicability. These frequency bands are particularly interesting to gain information on the permittivity of yeast cells in Glucose solution. Measurements from 240 GHz to 300 GHz were conducted with a continuous wave spectrometer from Toptica. At 7 GHz band, measurements have been performed using a rat-race based characterizing system realized on a printed circuit board. The conducted experiments demonstrate that by selecting the phase as characterization parameter, the presented contactless and label-free techniques are suitable for cell cultivation monitoring in a PTFE pipe based microfluidic system.
Journal of Physics Conference Series 04/2013; 434:012033.
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ABSTRACT: A passive microwave sensor based on microstrip lines for characterizing cell cultivation in aqueous compartments is presented. The proposed design methodology leads to a highly sensitive biosensor structure, which is fabricated on Rogers 3003 material. It is shown that a sufficiently high sensitivity is achieved to monitor the cultivation stadium of a yeast culture based on detection of permittivity changes. The obtained measurement results show good agreement with the performed full 3D EM simulations. According to these results the presented biosensor is capable of characterizing the stage of yeast cultivation label-free and contactless.
European Microwave Week, Amsterdam, Netherlands; 10/2012
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ABSTRACT: In this paper the design of integrated passive and active circuits in silicon by use of rigorous electromagnetic analysis. A broadband directional coupler has been designed with large bandwidth at 110 GHz center frequency and measured from 20 to 140 GHz. The simulation is compared to measurement showing very good agreement. A VCO has been designed at 116 GHz center frequency. The measurement of the center frequency is within 1% of simulation. The design methodology for a 240-GHz power detector also is given showing the design of a L-type matching network.
General Assembly and Scientific Symposium, 2011 XXXth URSI; 09/2011
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ABSTRACT: In this work, a 122 GHz transmitter circuit using frequency doublers is realized in 0.13 μm SiGe:C BiCMOS technology with f<sub>T</sub>/f<sub>max</sub> of 250/315 GHz. Two versions of the frequency doubler based on the balanced topology with cascode transistor are implemented. In the basic version, the peak conversion gain was -9 dB with -6 dBm output power. In the improved version the peak conversion gain is improved to -6 dB with -3 dBm peak output power by using open stubs as second harmonic reflectors. A transmitter is realized by combining a VCO working from 59-62 GHz with the basic version of the doubler. The transmitter output power is from -3.5 to -5.5 dBm in the output frequency range of 118-122 GHz.
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2011 IEEE 11th Topical Meeting on; 02/2011
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ABSTRACT: A fully integrated transmitter (TX) front-end for wireless communication at 60 GHz, produced in 0.25 μm SiGe:C BiCMOS technology is presented. The transmitter features a modified heterodyne topology with a sliding intermediate frequency (IF). The TX features IF I/Q mixers, an IF amplifier, a 60 GHz mixer, a phase-locked loop, an image-rejection filter and a power amplifier. The measured 1-dB compression point at the output is 12.6 dBm and the saturated power is 16.2 dBm. Error-free data transmission with a 16QAM OFDM signal and data rate of 3.6 Gbit/s (without coding 4.8 Gbit/s) over 15 m was demonstrated. This is the best reported result regarding both the data rate and transmission distance in SiGe without beamforming.
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2011 IEEE 11th Topical Meeting on; 02/2011
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ABSTRACT: In this paper directional couplers with reduced size, by lumped elements, inverted microstrip, and broadside coupled lines at 61, 110, and 122 GHz center frequency and up to 156-GHz bandwidth have been designed. The couplers show an isolation up to 40 dB. Different SiGe BiCMOS technologies with 250-nm and 130-nm feature width and 5 to 7 metal layers have been used. The measurement results have been compared to simulation results and good agreement has been observed.
Microwave Conference Proceedings (APMC), 2010 Asia-Pacific; 01/2011
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ABSTRACT: The paper presents 122 GHz receiver circuits including a low-noise-amplifier (LNA) and a mixer fabricated in SiGe BiCMOS technology. The design takes advantage of a novel transmission line structure with thick metal ground-shield on top of the MMIC. The LNA utilizes a two-stage cascode topology and the mixer is a Gilbert cell with additional current injection in the RF-path. Measurements of the receiver frontend show a gain of 12 dB and a noise figure below 13 dB at 121-129 GHz. The power consumption is 165 mW from a 3.5 Volt supply. The receiver frontend is intended for the use in ISM-band radar and communication systems, wide-band communication systems and in radar imaging systems.
Microwave Conference (EuMC), 2010 European; 10/2010
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ABSTRACT: The iterative design of an integrated subharmonic receiver for 120-127 GHz is presented. The receiver consists of a single-ended low-noise amplifier (LNA), a push-push voltage-controlled oscillator (VCO) with 1/32 divider, a polyphase filter, and a subharmonic mixer. The receiver is fabricated in SiGe:C BiCMOS technology with fT / f <sub>max</sub> of 255 GHz/315 GHz. In the first design the differential down-conversion gain of the receiver is 25 dB at 127 GHz, and the corresponding noise figure (NF) is 11 dB. The 3 dB bandwidth reaches from 125 GHz to 129 GHz. The input 1 dB compression point is at - 40 dBm. The receiver draws 139 mA from a supply voltage of 3.3 V. A subsequent design demonstrates 31 dB differential gain at 122 GHz, and 11 dB NF. The 3 dB bandwidth is from 121 GHz to 124 GHz. The receiver has a NF of 8 dB for 3 GHz IF frequency due to integrated RF bandpass-filtering. It is realized by the lower NF of the LNA, and the LNA itself.
IEEE Journal of Solid-State Circuits 10/2010; · 3.23 Impact Factor
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ABSTRACT: A subharmonic transceiver for sensing and imaging applications in the 122 GHz ISM band has been proposed. The receiver consists of a single-ended LNA, a push-push VCO with 1/32 divider, a polyphase filter, and a subharmonic mixer. The receiver is fabricated in SiGe:C BiCMOS technology with fT/fmax of 255GHz/315GHz. Its differential down-conversion gain is 31 dB at 122 GHz, and the corresponding noise figure is 11 dB. The 3-dB bandwidth reaches from 121 GHz to 124 GHz. The input 1-dB compression point is at -44 dBm. The receiver consumes 113 mA at a supply voltage of 3.2 V.
Microwave Symposium Digest (MTT), 2010 IEEE MTT-S International; 06/2010
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ABSTRACT: A 122 GHz subharmonic receiver for imaging and sensing applications has been realized, which consists of a single-ended LNA, a push-push VCO with 1/32 divider, a polyphase filter, and a subharmonic mixer. It is fabricated in SiGe:C BiCMOS technology with fT/fmax of 255 GHz/315 GHz. The down-conversion gain of the receiver is 25 dB at 127 GHz, and the corresponding noise figure is 11 dB. The 3-dB bandwidth reaches from 125 GHz to 129 GHz. The input 1-dB compression point is at -40 dBm. The receiver consumes 139 mA at a supply voltage of 3.3 V.
Bipolar/BiCMOS Circuits and Technology Meeting, 2009. BCTM 2009. IEEE; 11/2009
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ABSTRACT: The design of an integrated CMOS cascoded operational amplifier with two differential input stages is described. By using the nested Miller compensation the stability of the operational amplifier is ensured. The layout has been created automatically by using the ALADIN tool and prototype circuits have been fabricated. The small signal model for the amplifier is depicted and the test results are presented.
Mixed Design of Integrated Circuits & Systems, 2009. MIXDES '09. MIXDES-16th International Conference; 07/2009
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ABSTRACT: We present a single-chip fractional-N PLL for space applications. The design employs a high-current charge pump with optimum output biasing and a low-current charge pump for extension of the tuning range. We show that the extension of the tuning range does not increase phase noise and reference spurs. The PLL is tunable from 17.5 GHz to 18.9 GHz, and the phase noise at 1 MHz offset is below -110 dBc/Hz. Since loop bandwidth and phase noise are almost independent of the output frequency, the design is robust against parameter variations with process, voltage, temperature, and ageing.
Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE; 07/2009
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ABSTRACT: A fully integrated voltage-controlled oscillator (VCO) with a 17% tuning range and a low phase noise fabricated in a 0.25 mum SiGe BiCMOS technology is presented. To achieve a wide tuning range while keeping a low gain (K<sub>VCO</sub>), the VCO has 16 bands selectable by a 4-bit digital control. Coarse tuning is achieved using MOSFET varactors in a digital manner, which reduces the loss in the resonator. The measured phase noise is -111 dBc/Hz at 1 MHz offset from a 22 GHz carrier. This phase noise level is believed to be the lowest reported so far for an integrated silicon-based VCO in the 20-30 GHz frequency band.
Electronics Letters 02/2009; · 0.96 Impact Factor
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Chang-Soon Choi,
E. Grass,
F. Herzel,
M. Piz, K. Schmalz,
Yaoming Sun,
S. Glisic,
M. Krstic,
K. Tittelbach,
M. Ehrig,
W. Winkler,
R. Kraemer,
C. Scheytt
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ABSTRACT: We present 60 GHz OFDM hardware demonstrators developed so far and outline design considerations for future developments. OFDM schemes have been developed to combat multi-path interferences in indoor wireless environments and further optimized for multi-gigabit data transmission in 60 GHz-band. RF and IF analogues front-ends (AFEs) have been developed with high-speed SiGe BiCMOS technologies. Future developments on AFE are mainly devoted to one-chip integration of RF and IF components based on a sliding IF architecture. We have already achieved wireless transmission of about 1 Gbps in an OFDM demonstrator, which will be continuously upgraded and optimized for higher data transmission with better link adaptability.
Personal, Indoor and Mobile Radio Communications, 2008. PIMRC 2008. IEEE 19th International Symposium on; 10/2008
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R. Follmann,
D. Kother,
T. Kohl,
M. Engels,
T. Podrebersek,
V. Heyer, K. Schmalz,
F. Herzel,
W. Winkler,
S. Osmany,
U. Jagdhold
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ABSTRACT: Broad band satellite communication makes high demands on linear low phase noise signals. One example is HDTV. For this application converters are required (e.g. from 30 GHz to 20 GHz), which themselves require very low phase noise programmable synthesizers (LO). Most satellite companies today derive their 10 GHz LOs from multiplying a 100 MHz crystal oscillator again and again. Due to the arising sub-harmonics excessive filtering is required. Thus, today's satellite LOs are large and quite heavy in weight. In this paper we demonstrate a single chip SiGe integrated fractional-N PLL, which can either be used with the internal integrated VCO between 18.5 and 20.0 GHz or with any external VCO between 275 MHz...20 GHz. The LO presented fulfills the high demands on phase noise for satellite applications. Furthermore, first radiation hardness steps such as triple model redundancy have already been implemented.
Microwave Symposium Digest, 2008 IEEE MTT-S International; 07/2008
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ABSTRACT: We present a dual-loop PLL architecture for low-noise frequency synthesizers. The approach is experimentally verified for a 48 GHz PLL in 0.25 mum SiGe BiCMOS technology intended for a 60 GHz wireless transceiver. The design employs two parallel charge pumps one of which dominates the loop dynamics and is biased at optimum output voltage. This equalizes the loop bandwidth and reduces charge pump mismatch.
Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008. IEEE Topical Meeting on; 02/2008
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ABSTRACT: We present a fully integrated phase-locked loop tunable from 17.5 GHz to 19.2 GHz fabricated in a 0.25 mum SiGe BiCMOS technology. The measured phase noise is below -110 dBc/Hz at 1 MHz offset over the whole tuning range. Based on an integer-N architecture, the synthesizer consumes 248 mW and occupies a chip area of 2.1 mm including pads. Quadrature outputs at quarter of the oscillator frequency are produced, which are required in a sliding-IF 24 GHz transceiver. Possible applications include wireless LAN as well as satellite communication. The measured phase noise is the lowest among previously published Si-based integrated synthesizers above 12 GHz.
Compound Semiconductor Integrated Circuit Symposium, 2007. CSIC 2007. IEEE; 11/2007
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ABSTRACT: The communication market demands broadband transmission, high density television (HDTV) and interactivity, whereby HDTV will become the leading application. All applications require a high number of individual channels, leading to a large number of up-and down-converters. These high needs can be served best with highly integrated SiGe MMICs. It has been demonstrated that the best suited RF-element to be developed is the local oscillator (LO) synthesizer, which fits well to the SiGe technology. The most critical building blocks of the LO are the voltage controlled oscillator (VCO) which is challenging in its phase noise behavior and the fractional-N' divider with its large influence on phase noise and spurs. This paper will describe the flexible design of a MMIC, which can be used also as a PLL circuit together with an external oscillator in a broad frequency range.
Microwave Integrated Circuit Conference, 2007. EuMIC 2007. European; 11/2007
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E. Grass,
F. Herzel,
M. Piz, K. Schmalz,
Yaoming Sun,
S. Glisic,
M. Krstic,
K. Tittelbach,
M. Ehrig,
W. Winkler,
C. Scheytt,
R. Kraemer
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ABSTRACT: This paper reports implementation details of a 60 GHz short range communication system for data rates up to 2 Gbit/s. Based on a MATLAB model the main PHY parameters were derived, and the modules of the analog frontend were specified. For system verification, a demonstrator was developed. The analog RF and IF circuits of the demonstrator are implemented in a 0.25 mum SiGe BiCMOS technology. Measurement results of the analog modules and the complete demonstrator are given. Using OFDM modulation, the maximum data rate transmitted via airlink so far, is 960 Mbit/s.
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007
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ABSTRACT: This paper presents a wideband I/Q upconverter and an I/Q downconverter for the 5 GHz band, which are integrated with a programmable 5 GHz phase-locked loop for I/Q generation. The quadrature signals are derived from a 10 GHz CMOS VCO followed by a bipolar frequency divider. The image rejection of the upconverter is as low as -38 dBc for an input frequency of 100 MHz. Phase noise at 1 MHz at the upconverter output is below -112 dBc/Hz. The two chips were produced in a 0.25 mum SiGe BiCMOS technology. They will be part of an integrated heterodyne 60 GHz wideband transceiver with 1 Gbit/s data rate
Wireless Technology, 2006. The 9th European Conference on; 10/2006
