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ABSTRACT: Junctionless transistors are variable resistors controlled by a gate electrode. The silicon channel is a heavily doped nanowire
that can be fully depleted to turn the device off. The electrical characteristics are identical to those of normal MOSFETs,
but the physics is quite different. This paper compares the conduction mechanisms in three types of MOS devices: inversion-mode,
accumulation-mode and junctionless MOSFET.
12/2010: pages 187-200;
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ABSTRACT: The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability current (I<sub>WR</sub>) of 33 A along with a low leakage current (I<sub>LEAK</sub>) of 2 pA at a supply voltage (V<sub>DD</sub>) of 0.9 V for cell and pull-up ratios of 1. Results offer a new opportunity to design future SRAM cells with nanoscale JL MOSFETs.
Electronics Letters 11/2010; · 0.96 Impact Factor
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ABSTRACT: Conduction mechanisms in junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.
Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European; 10/2010
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ABSTRACT: We investigate planar fully depleted silicon-on-insulator(SOI) MOSFETs with a thin buried oxide (BOX) and a ground plane (GP). To study the depletion effects in the lightly doped drain (LDD) and substrate, we compare different BOX/GP/ LDD structure combinations. A novel GP back-gate engineering approach is introduced to improve both short-channel effects (SCEs) and LDD resistance. In this technique, an LDD/channel/ LDD mirror doping structure is reproduced in the back gate underneath the thin BOX. It is shown that SCEs are rather insensitive to SOI layer thickness variations and remain well controlled for gate lengths down to 15 nm for both nMOS and pMOS transistors due to outstanding electrostatic control: 63 mV/dec subthreshold swing and 7 mV/V drain-induced barrier lowering at V<sub>dd</sub> = 1 V. The shift of the threshold voltage ΔV<sub>th</sub> with silicon film thickness Tsi down to 0.5 mV/nm is obtained. Simulations show that a 20% reduction in LDD resistance can be achieved in thin BOX devices with an optimized GP, as compared with thick BOX transistors. In addition, an improvement in drive current is also reported.
IEEE Transactions on Electron Devices 07/2010; · 2.32 Impact Factor
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ABSTRACT: This paper investigates the temperature dependence of the main electrical parameters of junctionless (JL) silicon nanowire transistors. Direct comparison is made to silicon nanowire (trigate) MOSFETs. Variation of parameters such as threshold voltage and on-off current characteristics is analyzed. The JL silicon nanowire FET has a lager variation of threshold voltage with temperature than the standard inversion- and accumulation-mode FETs. Unlike in classical devices, the drain current of JL FETs increases when temperature is increased.
IEEE Transactions on Electron Devices 04/2010; · 2.32 Impact Factor
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ABSTRACT: In this paper, we report the possibility of achieving sub-kT/q subthreshold slope (i.e. lower than 59.6 mV/decade at T=300 K) without using either impact ionization or band-to-band tunneling. The device uses intraband tunneling within the conduction band through barriers whose shape varies with the applied gate voltage. Subthreshold slope as low as 56.5 mV/decade is reported at T=300 K. The VBT reported here breaks the 60 mV/dec barrier over more than five decades of subthreshold current, which is the highest current range reported so far.
SOI Conference, 2009 IEEE International; 11/2009
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J.P. Colinge,
C.W. Lee,
A. Afzalian,
N. Dehdashti, R. Yan,
I. Ferain,
P. Razavi,
B. O'Neill,
A. Blake,
M. White,
A.M. Kelleher,
B. McCarthy,
R. Murphy
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ABSTRACT: We report the fabrication of junctionless SOI MOSFETs. Such devices greatly simplify processing thermal budget and behave as regular multigate SOI transistors.
SOI Conference, 2009 IEEE International; 11/2009
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ABSTRACT: In this paper, we analyze LDD depletion effects in fully-depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). LDD engineering is introduced to reduce the source and drain resistance and threshold voltage shifts. Short-channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15 nm.
SOI Conference, 2009 IEEE International; 11/2009
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C.-W. Lee,
I. Ferain,
A. Afzalian,
K.-Y. Byun, R. Yan,
N. Dehdashti,
P. Razavi,
W. Xiong,
J.P. Colinge,
C.A. Colinge,
D.E. Ioannou
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ABSTRACT: The results are reported of an experimental study of the hot carrier (HC) and bias-temperature-instability (BTI) reliability of MuGFETS, fabricated on SOI wafers with silicon oxide and silicon nitride buried layers. N- and P-channel devices of 65 nm long and 42 nm or 32 nm wide channels were stressed and measured at room temperature and at 125degC. A complicated picture emerges: HC degradation is dominant in n-MuGFETs whereas both HC and BTI mechanisms are active concurrently in p-MuGFETs under hot carrier stress. When HC degradation dominates, the wider fin devices tend to degrade more than the narrower; the reverse is generally true for BTI degradation.
Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European; 10/2009
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ABSTRACT: We present here 3D quantum simulations based on non-equilibrium Green's function (NEGF) formalism using the Comsol Multiphysicstrade software and on the implementation of a new fast coupled mode-space (FCMS) approach. The FCMS algorithm allows one to simulate transport in nanostructures presenting discontinuities, as the normal coupled mode-space (CMS) algorithm does, but with the speed of a fast uncoupled-mode space (FUMS) algorithm (a faster algorithm that cannot handle discontinuities). Using our simulator, we also show that energy barriers resulting from cross-section variations at the gate edge of a nanowire can be optimized to improve the on/off current ratio. A subthreshold slope steeper than the kT/q.log(10) limit of classical transistors together with symmetrical source-drain operation is demonstrated for the first time using this new variable barrier tunnel transistor (VBT) concept.
Simulation of Semiconductor Processes and Devices, 2009. SISPAD '09. International Conference on; 10/2009
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ABSTRACT: We have investigated the effect of symmetric geometrical constrictions on the device characteristics of ultrathin silicon-on-insulator (SOI) nanowire with Trigate structure by means of the full real-space three dimensional Nonequilibrium Greens's Function (NEGF) method. In this study, geometrical constrictions are introduced as energy barriers near the source and the drain junctions and their strength is modulated by the potential height and the geometry. Interestingly, even at room temperature the drain current in the device shows oscillations as a function of the applied gate voltage. This can be traced to the development of transmission resonances as the channel is additionally confined along the current direction.
Computational Electronics, 2009. IWCE '09. 13th International Workshop on; 06/2009
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ABSTRACT: This paper analyzes the drain breakdown voltage of multigate MOSFETs and the influence of parameters such as doping concentration, fin width, and gate length. The good electrostatic control of the active area by the multigate structure improves the drain breakdown voltage, which increases as the fin width is decreased. Increasing the channel doping concentration improves the drain breakdown voltage as well.
IEEE Transactions on Electron Devices 01/2009; · 2.32 Impact Factor
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ABSTRACT: The performances of accumulation-mode and inversion-mode multigate FETs are compared. Both simulation and experimental data are presented. Accumulation-mode devices have a higher current drive and less process variability than inversion-mode FETs.
Silicon Nanoelectronics Workshop, 2008. SNW 2008. IEEE; 07/2008
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ABSTRACT: The origin of the large Vt shift observed in planar FDSOI is the creation of negative charge states in the BOX by F implant. F implant is a suitable approach for planar FDSOI SoC integration with single WF metal gate, but NOT for MuGFETs. F implant degrades electron mobility and the degradation is a function of F dose. The hole mobility is unaffected by F implant.
SOI Conference, 2007 IEEE International; 11/2007
