R. Zanbaghi

Sharif University of Technology, Teheran, Tehrān, Iran

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Publications (6)0 Total impact

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    ABSTRACT: The design of a complex active-RC filter for low-IF wireless applications is described. Fifth-order complex Butterworth filter is designed using class-AB operational amplifier architecture. This new structure makes the filter suitable for low power applications with high dynamic range. Simulation results show that the filter provides more than 40 dB image rejection ratio (IIR) and dynamic range of 82 dB. The complete filter including on-chip tuning circuit consumes only 4.3 mW with 1.8 V single supply voltage.
    Integrated Circuits, 2007. ISIC '07. International Symposium on; 10/2007
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    ABSTRACT: A fully integrated CMOS base-band part of a low-IF WPAN receiver is presented, which consists of an active complex filter, an automatic gain control unit, and a 10-bit pipeline ADC. The highlights of the receiver include a low-power active complex filter with a new g<sub>m </sub>-C filter structure and a high-resolution, low power pipeline ADC using averaging and double sampling techniques. The chip was designed using 0.18-mum standard CMOS process. The filter provides more than 55-dB image rejection ratio and IM3 of -50-dB for 0.2-Vpp input signal. The converter has a peak SFDR of 61 dB, maximum DNL of 0.5 LSB, and INL of 0.9 LSB. The whole circuit draws 4-mA from a 1.8-V power supply
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007
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    ABSTRACT: A fully integrated CMOS base-band part of a low-IF WPAN receiver is presented, which consists of an active complex filter, an automatic gain control unit, and a 10-Bit Pipe-Line ADC. The highlights of the receiver include a low-power active complex filter with a nonconventional Gm-C structure and a high-resolution, low power pipe line ADC using averaging and double sampling techniques. The chip was designed on a small die using 0.18-um standard CMOS process. The filter provides more than 55 db image rejection ratio and IM3 of -50 dB for 1.9 & 2.1 MHz signals with 0.2Vpp. The converter has a peak SFDR of 61 dB, maximum DNL of 0.5 LSB, and INL of 0.9 LSB. The all parts of the scheme consume an active current about 4mA from a 1.8-V power supply.
    Microelectronics, 2006. ICM '06. International Conference on; 01/2007
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    ABSTRACT: The design of a Gm-C filter for High-Frequency applications is described in this paper. A low-pass, sixth-order elliptic Gm-C filter based on the new biquadratic architecture in 0.18 um CMOS process is designed with the proper dynamic rang. A simple structure of the high Q biquadratic filter is used to enhance the linearity and tunability of the filter. The cut off frequency of this filter is 33 MHz. It has a THD of -45 dB for 0.2 Vpp, 8 MHz signal. The complete filter including on-chip tuning circuit consumes only 0.8 mA with 1.8 V single supply voltage.
    Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on; 01/2007
  • R. Zanbaghi, M. Atarodi, S. Mehrmanesh
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    ABSTRACT: A 1.8 V, 10-Bit, 40-MS/s pipeline analog-to-digital converter designed using 0.18-mum CMOS technology is presented. The new structure of the A/D converter is based on double sampling and averaging techniques. By the first technique, all the stage amplifiers are active at the both sampling and holding cycles. Averaging as the second technique minimizes the capacitance mismatch and exchanges the priority of input-referred noise and capacitance mismatch in the selection of the stage caps. The converter achieved a peak spurious-free-dynamic-range of 61 dB, maximum differential nonlinearity 0.5 of least significant bit (LSB), maximum integral linearity of 0.9 LSB, and power consumption of 5 mW
    01/2006;
  • R. Zanbaghi, M. Atarodi, A. Tajalli
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    ABSTRACT: The design of a Gm-C complex filter for low-IF WPAN applications is described. Sixth-order complex Butterworth filter is designed using a simple architecture of the transconductance in the desired Gm-C filter. This new structure makes the filter suitable for high frequency applications with proper dynamic range, lower power, and minimum die area. Simulation results show that the filter provides more than 55 dB image rejection ratio (IIR) and IM3 of -50 dB for 1.9 & 2.1 MHz signals with 0.2 Vpp. The complete filter including on-chip tuning circuit consumes only 0.4 mA with 1.8 V single supply voltage
    01/2006;