ABSTRACT: A new design of an integrated two-stage class-F power amplifier (PA) for wireless application operating in the 1.65 GHz frequency range is described. The circuit utilizes a simple method to drive the output stage with a half sinusoidal waveform that is optimal for class-F operation. The circuit was fabricated in a Silterra's standard 0.18 mum RF CMOS technology. Measurement result shows a maximum power-added efficiency (PAE) of 42% and a maximum gain of 19.7 dB. When operating from a 3 V voltage supply, the PA delivers an output power of 18.9 dBm. This work demonstrates the feasibility of using class-F PAs for short-range and low-power applications.
Integrated Circuits, 2007. ISIC '07. International Symposium on; 10/2007
ABSTRACT: This work will explore the integration of a class-F power amplifier using CMOS technology. At 2.4 GHz, the fully integrated on-chip CMOS power amplifier can deliver 21.8 dBm output power with 43.95% efficiency. The design makes use of the C18 RF models provided by Silterra and design of spiral inductor using commercial synthesis software.
Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on;