Chung-Chih Hung

National Chiao Tung University, Hsin-chu-hsien, Taiwan, Taiwan

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Publications (65)33.29 Total impact

  • Fang-Ting Chou, Chia-Min Chen, Chung-Chih Hung
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    ABSTRACT: This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers to drive a lot of current switches and re-timing latches, the proposed design uses variable-delay buffers with a compact layout to compensate for the delay difference among different bits, and to reduce glitch energy from 132 to 1.36 pV s during major code transitions. The measured spurious free dynamic range (SFDR) has been improved over 10 dB, as compared to DACs without variable-delay buffers. At 250 MS/s update rate, the proposed DAC achieves 56 dB SFDR for 0.67 MHz output frequency and 49 dB SFDR for 94 MHz output frequency with 50 Ω termination. For static performance, the measured integral nonlinearity (INL) and differential nonlinearity (DNL) is less than 1.6 and 1.8 LSB, respectively. The proposed DAC can be used in various applications in industry, including digital video, digital TV, wireless communication system, etc. This chip was implemented in TSMC 1P6M 0.18 μm CMOS technology and dissipates 19 mW from a single 1.8 V power supply.
    Analog Integrated Circuits and Signal Processing 05/2014; 79(2). · 0.55 Impact Factor
  • Chia-Min Chen, Chung-Chih Hung
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    ABSTRACT: This paper presents a novel frequency compensation technique for a low-dropout (LDO) voltage regulator. Enhanced active feedback frequency compensation is employed to improve the frequency response. The proposed LDO is capable of providing high stability for current loads up to 150 mA with or without loading capacitors. The proposed LDO voltage regulator provides a loop bandwidth of 7.8 MHz under light loads and 6.5 MHz under heavy loads. The maximum undershoot and overshoot are 59 and 90 mV, respectively, for changes in load current within a 200-ns edge time, while the compensation capacitors only require a total value of 7 pF. This enables easy integration of the compensation capacitors within the LDO chip. The proposed LDO regulator was designed using TSMC 0.35-μm CMOS technology. With an active area of 0.14 mm2 (including feedback resistors), the quiescent current is only 40 μA. The input voltage ranges from 1.73 to 5 V for a loading current of 150 mA and an output voltage of 1.5 V. The main advantage of this approach is the stability of the LDO circuit when external load capacitors are connected, or even without load capacitors.
    Analog Integrated Circuits and Signal Processing 04/2013; 75(1). · 0.55 Impact Factor
  • Chia-Min Chen, Kai-Hsiu Hsu, Chung-Chih Hung
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    ABSTRACT: This paper presents a freewheel-charge-pump-controlled design for a single-inductor multiple-output (SIMO) DC–DC Converter. By applying the freewheel-charge-pump-controlled (FCPC) technique, the freewheel switching time is reused, and two extra charge-pump outputs are provided by time recycling, with no cost in time sequences. The converter has two step-up outputs and two charge-pump outputs that can be higher or lower than the input supply. The converter utilizes a 1 μH inductor, 4.7 μF charge-pump capacitors and 33 μF output capacitors at a frequency of 1 MHz. The proposed converter shows low cross-regulation and achieves a maximum loading current of 70 mA. Fabricated in a 0.18-μm CMOS process, the proposed circuit occupies 1.3 × 1.3 mm2. Experimental results demonstrate that the converter successfully generates four well-regulated outputs with a single inductor. The supply voltage ranged from 1.6 to 2.5 V and the load regulation performance was 0.08, 0.05, 1.7, and 1.9 mV/mA for VO1, VO2, VO3 and VO4, respectively.
    Analog Integrated Circuits and Signal Processing 01/2013; 74(1). · 0.55 Impact Factor
  • Jun-Ren Su, Te-Wen Liao, Chung-Chih Hung
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    ABSTRACT: This paper proposes an all-digital fast-locking pulsewidth-control circuit with programmable duty cycle. In comparison with prior state-of-the-art methods, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay cells, while maintaining the same level of accuracy. This paper presents a new duty-cycle setting circuit that calculates the desired output duty cycle without the need for a look-up table. The circuit was fabricated under the two-stage matrix converter 0.18-CMOS process. Results show that the proposed circuit performs well for an input operating frequency ranging from 200 to 600 MHz, and an input duty cycle ranging from 30% to 70%. It achieves a programmable output duty cycle ranging from 31.25% to 68.75% in increments of 6.25%.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2013; 21(6):1154-1164. · 1.22 Impact Factor
  • Chia-Min Chen, Tung-Wei Tsai, Chung-Chih Hung
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    ABSTRACT: This brief presents a low-dropout (LDO) voltage regulator without output capacitors that achieves fast transient responses by hybrid dynamic biasing. The hybrid dynamic biasing in the proposed transient improvement circuit is activated through capacitive coupling. The proposed circuit senses the LDO regulator output change so as to increase the bias current instantly. The proposed circuit was applied to an LDO regulator without output capacitors implemented in standard 0.35- μm CMOS technology. The device consumes only 25 μA of quiescent current with a dropout voltage of 180 mV. The proposed circuit reduces the output voltage spike of the LDO regulator to 80 mV when the output current is changed from 0 to 100 mA. The output voltage spike is reduced to 20 mV when the supply voltage varies between 1.3 and 2.3 V with a load current of 100 mA.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2013; 21(9):1742-1747. · 1.22 Impact Factor
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    ABSTRACT: This paper presents an inductorless dual-output switched-capacitor DC-DC converter employing pseudo-three-phase swap-and-cross control (PTPSCC) and an amplitude modulation mechanism (AMM). The AMM circuit scales the amplitudes of the driving signals for the switches according to the loading conditions in order to minimize switching losses. To reduce output ripples, average charge distribution, and improve regulation, the PTPSCC circuit continuously switches power transistors to deliver enough charge to the outputs by keeping at least one flying capacitor connected to each output. The two outputs were regulated at 2.5 V and 0.8 V with input ranges of 1.7-2 V. The maximum output loading was 100 mA for both outputs. A power efficiency of 90.5% was achieved at a maximum total output power of 330 mW with a switching frequency of 500 kHz. The maximal peak-to-peak output ripple voltages for the two outputs under 100 mA load currents were suppressed to below 26 mV and 20 mV, respectively.
    Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian; 01/2013
  • Te-Wen Liao, Jun-Ren Su, Chung-Chih Hung
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    ABSTRACT: This paper presents a frequency synthesizer system with random pulsewidth matching technique and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5 GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90-nm CMOS process. The proposed circuit can achieve a phase noise of -114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below -74 dBc.
    Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on; 01/2013
  • Te-Wen Liao, Jun-Ren Su, Chung-Chih Hung
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    ABSTRACT: This brief presents a low-spur phase-locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator to reduce the reference spur at the output of the PLL. A novel random clock generator is presented to perform the random selection of the phase frequency detector control for the charge pump in locked state. The proposed frequency synthesizer was fabricated in a TSMC 0.18-μm CMOS process. The proposed PLL achieved phase noise of -93 dBc/Hz with a 600-kHz offset frequency and reference spurs below -72 dBc.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2013; 21(3):589-592. · 1.22 Impact Factor
  • Te-Wen Liao, Jun-Ren Su, Chung-Chih Hung
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    ABSTRACT: This paper presents a low phase-noise phase locked loop (PLL) system with a Multi-Phase Over-Sampling Charge Pump (MPOSCP) for wireless applications. The low phase-noise frequency synthesizer reduces ripples and noise on the control voltage of the ring voltage-controlled oscillator (VCO) as a means to control in-band noise at the output of the PLL. An MPOSCP is proposed to perform multi-phase over-sampling control for the charge pump (CP) in locked state. The proposed frequency synthesizer was fabricated using the TSMC 90-nm CMOS process. The prototype occupies 0.046mm2 active area, the reference frequency is 27 MHz, and the output frequency is 432 MHz with the total power consumption of 7 mW. The PLL achieved phase noise below -100 dBc/Hz from 15 Hz to 100 kHz with the reference spurs below-48 dBc.
    Circuits and Systems (ISCAS), 2013 IEEE International Symposium on; 01/2013
  • Tien-Yu Lo, Chung-Chih Hung
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    ABSTRACT: A high speed and high linearity Gm-C low-pass filter is presented. The proposed OTA is designed under low power supply voltage consideration while its gain, excess phase, and linearity are well maintained. The common-mode control system, including common-mode feedback and common-mode feedforward circuits, is added to ensure stability of the proposed filter. Measurement results show that the inter-modulation distortion of −40 dB can be achieved with 250 MHz 400 mVpp balanced differential input signals. The filter works in 1 − V supply voltage and its power consumption is 32 mW.
    Analog Integrated Circuits and Signal Processing 06/2012; · 0.55 Impact Factor
  • Tien-Yu Lo, Chung-Chih Hung
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    ABSTRACT: A CMOS transconductor for wide tuning range filter application is presented. The linear transconductor is designed based on the flipped-voltage follower (FVF) circuit and can work in the weak, moderate, and strong inversion regions to maximize the transconductance tuning range. The transconductance tuning can be achieved by changing the bias current of the active resistor, and a ratio of 28 is obtained. The transconductor was evaluated by using TSMC 0.18 μm CMOS process, and the total harmonic distortion (THD) of −56 dB can be obtained by giving a 12 MHz 0.4 Vpp input swing signal. In the design, the maximum power consumption is 2 mW with the transconductance of 1.1 mS under a 1.8 V supply voltage.
    Analog Integrated Circuits and Signal Processing 04/2012; 71(1). · 0.55 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a freewheel-charge-pump-controlled design for a single-inductor multiple-output (SIMO) DC-DC Converter. By applying the freewheel-charge-pump-controlled (FCPC) technique, the freewheel switching time is reused, and two extra charge-pump outputs are provided by time recycling, with no cost in time sequences. The converter has two step-up outputs and two charge-pump outputs that can be higher or lower than the input supply. The proposed converter shows low cross-regulation and achieves a maximum loading current of 70 mA. Fabricated in a 0.18-μm CMOS process, the proposed circuit occupies only 1.3×1.3 mm2. Experimental results demonstrate that the converter successfully generates four wellregulated outputs with a single inductor. The supply voltage ranged from 1.6 V to 2.5 V and the load regulation performance was 0.08 mV/mA, 0.05mV/mA, 1.7 mV/mA, and 1.9 mV/mA for VO1, VO2, VO3 and VO4, respectively.
    ESSCIRC (ESSCIRC), 2012 Proceedings of the; 01/2012
  • Te-Wen Liao, Chia-Min Chen, Jun-Ren Su, Chung-Chih Hung
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    ABSTRACT: This paper presents a fast locking phase-locked loop (FLPLL) system with reference-spur reduction techniques exploiting random pulsewidth matching and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. The loop bandwidth of the system can be adjusted by the control voltage so as to reduce the locking time. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5 GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90-nm CMOS process. The proposed circuit can achieve a phase noise of -114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below -74 dBc.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 01/2012; 59(12):2815-2824. · 2.24 Impact Factor
  • Te-Wen Liao, Jun-Ren Su, Chung-Chih Hung
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    ABSTRACT: In this paper, we presents a low-spur phase locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator (VCO) in order to reduce the reference spur at the output of the PLL. A new random clock generator is presented to perform a random selection of phase frequency detector (PFD) control for charge pump at locked state. The proposed frequency synthesizer was fabricated in TSMC 0.18-μm CMOS process. The PLL has achieved the phase noise of -105 dBc/Hz at 1MHz offset frequency and reference spurs below -72dBc.
    Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on; 01/2012
  • Tien-Yu Lo, Chung-Chih Hung
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    ABSTRACT: A continuous-time fourth-order equiripple linear phase filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined common-mode feedforward and common-mode feed- back circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining an equivalent negative resistor circuit at the output nodes. Transcon- ductance tuning can be achieved by adjusting the bulk voltage by using the deep-NWELL technology. The modified automatic tuning circuit relaxes the speed requirement of the tuning blocks. Through the use of the operational transconductance amplifier as a building block with the automatic tuning scheme, the filter 3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The 43 dB of IM3 at filter cutoff frequency is obtained with 4 dbm two-tone signals. Implemented in 0.18- m CMOS process, the chip occupies 1 mm and consumes 175 mW at a 1.5-V supply voltage.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2011; 19:175-181. · 1.22 Impact Factor
  • Chia-Min Chen, Chung-Chih Hung
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    ABSTRACT: A fast self-reacting (FSR) low-dropout (LDO) regulator with triple transient improved loops was implemented in 0.35μm CMOS technology. The proposed regulator for SoC application can achieve high stability for load current from zero to 100mA. The FSR loops can accelerate load transient responses while the regulator achieves the FOM of only 0.00675 (ps) without an output capacitor. The experimental results show the load regulation of 75.2 μV/mA and line regulation of 1.046 mV/V. The whole LDO chip consumes a quiescent current of 27 μA with an ultra low dropout voltage of 142mV at the maximum output current of 100mA. The proposed FSR transient improved loops can effectively reduce the transient voltage undershoot and overshoot. While the load current switches between 0 and 100 mA with both rise and fall time of 1 μs, the result shows that the maximum undershoot is 25 mV and that the maximum overshoot is 5 mV. When the full load current is 100mA, the undershoot and the overshoot of the line transient response are 4 mV and 6.5 mV, respectively, for a 1 V step supply waveform with 5 μs transient time.
    Proceedings of the 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, Sept. 12-16, 2011; 01/2011
  • Tien-Yu Lo, Chung-Chih Hung, Chi-Hsiang Lo
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    ABSTRACT: This paper presents a high linearity MOSFET-only transconductor based on differential structures. While a precise BSIM4 transistor model is introduced through analysis, the linearity can be improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. When the compensation utilizes transistors in subthreshold region, rather than the transistors in saturation region, the value of transconductance can be maintained. The circuit is fabricated in TSMC 0.18-μm CMOS process. The measurement results show 18dB improvement of the proposed version, and 65dB HD3 can be achieved for a 2.1MHz 700mVpp differential input. The static power consumption under 1-V power supply voltage is 183μW. Measurement results demonstrate the agreement with theoretical analyses. KeywordsTransconductor–Subthreshold–THD
    Analog Integrated Circuits and Signal Processing 01/2011; 66(1):1-7. · 0.55 Impact Factor
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    ABSTRACT: A Phase-based Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) adopting a Delay-Locked-Loop (DLL) mechanism is presented. It is realized by a modification of a DLL using a Voltage-Controlled Delay Line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed ΔΣ ADC achieved 7.99 bits resolution with OSR =32 for a 10 MHz signal bandwidth.
    01/2011;
  • Chia-Min Chen, Kai-Hsiu Hsu, Chung-Chih Hung
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    ABSTRACT: This paper presents a high efficiency current-mode DC-DC step-down converter with wide range of output current. The converter adaptively operates as Pulse-Width Modulation (PWM). An on-chip current sensing technique is employed to reduce external components and no extra I/O pins are needed for the current-mode controller. A soft-start operation is designed to eliminate the excess large current during the startup of the regulator. The circuit has been designed with TSMC 2P4M 0.35 μm CMOS process. The range of the supply voltage is from 2 to 5V, which is suitable for single-cell lithium-ion battery.
    Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on; 09/2010
  • Zhe-Yang Huang, Chung-Chih Hung
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    ABSTRACT: A 1V 4.8mW 42.6GHz-45.6GHz CMOS Voltage Controlled Oscillator (VCO) is designed for IEEE 802.15.3c mm-wave wireless communication system. The oscillator provides a center frequency of 44.1GHz and is implemented in 90nm Logic CMOS technology. The oscillator core consumes 4.8mW through 1.0V supply voltage and the active area is 0.05mm2 only. A tuning range of 3.0GHz (42.6GHz-45.6GHz) with maximum control voltage of 1.0V can be achieved. And the phase noise is -93.7 dBc/Hz at 1MHz offset from the center frequency. The calculated figure-of-merit (FOM) is -180.1 dB.
    01/2010;

Publication Stats

261 Citations
33.29 Total Impact Points

Institutions

  • 2006–2014
    • National Chiao Tung University
      • • Department of Electronics Engineering
      • • Institute of Communications Engineering
      Hsin-chu-hsien, Taiwan, Taiwan
  • 2008–2009
    • MediaTek
      Hsin-chu-hsien, Taiwan, Taiwan
  • 1995–1999
    • The Ohio State University
      • Department of Electrical and Computer Engineering
      Columbus, OH, United States
  • 1996–1997
    • University of Helsinki
      Helsinki, Southern Finland Province, Finland