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ABSTRACT: An ultra-low power (ULP) SoC including an IEEE802.15.4 2.4 GHz transceiver designed in 130 nm CMOS technology is presented. Power consumption was minimized by using a concurrent system and design optimization to avoid the over-specification of blocks. A novel minimum complexity partial correlation algorithm is used in the digital baseband receiver and drains an average of 4802 A (packet PSDU=20 bytes). At 1.2 V, the transceiver drains 5.4 mW and 8.1 mW in RX and TX active modes, respectively, and achieves 1% PER for a -81 dBm input power. For a 250 kbit/s data rate, the transceiver attains an energy efficiency of 21.5 nJ/bit RX and 32.5 nJ/bit TX.
Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European; 10/2008
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ABSTRACT: This paper explores new capabilities brought on by Independently Driven Double Gate CMOS transistors (IDGMOS) for analog baseband design. Since the gates are disconnected, the corresponding channels are coupled resulting in a dynamic threshold voltage tuning. This operation mode is exploited to create new analog functions and low-voltage circuits. A current mirror is redesigned using IDGMOS and it is shown that this structure performs an efficient differential function relating to the potentials applied to the back gates. Being adapted to low-voltage operation and self compensated from input common-mode variations, the differential current mirror is employed for the active loading of a low-voltage fully-balanced OTA. It then improves the limited common-mode rejection of the original OTA structure by providing output feed-back and input feed-forward compensation.
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on; 01/2008
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ABSTRACT: This paper reviews two basic analog circuits that employ new capabilities brought about by independently driven double gate CMOS transistors (IDGMOS). The subject of the first review is a 1 V supply voltage follower that uses IDGMOS to increase the input range up to the supply voltage and to enhance the biasing circuit of the follower. The second looks at a new general method to make fully balanced differential amplifiers (FBAs) with compact common-mode feed back. IDGMOS FBAs perform complete transistor reuse without using any extra device to execute the feed-back amplifier functions, i.e. error evaluation and amplification. An application of this is illustrated with the simulation of a simple 1-stage differential amplifier with 38 dB gain and a 90.3 degree phase margin. The complete feed back loop includes the aforementioned voltage follower. The common-mode open loop gain is only about 21 dB but the common-mode reference voltage range, within 10% relative error, remains between 0.3 V and 0.9 V.
Research in Microelectronics and Electronics Conference, 2007. PRIME 2007. Ph.D.; 08/2007
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ABSTRACT: In this paper, we present an integrated upconversion stage including an integer-N synthesizer in a 0.35 μm BiCMOS process. This chip is, to our knowledge, the first integrated circuit for a DVB-RCT application ever published. This standard requires 125 kHz frequency steps in the UHF band and an architecture is proposed to upconvert the 44 MHz IF signal. The realization of a converter stage, composed of a mixer and a synthesizer, based on a multiband VCO (voltage controlled oscillator), is also described. The mixer converts frequencies from 1080-1092 MHz to the UHF band (470-860 MHz). The synthesizer includes a programmable divider, with a dual modulus prescaler, and a multiband LC-VCO, which allows a frequency range of 1550-1952 MHz. A single side band phase noise of -84 dBc/Hz at 10 kHz offset and -122 dBc/Hz at 1 MHz offset have been measured at the synthesizer output. A power conversion gain of 7 dB and a noise figure of 14.9 dB characterize the mixer.
Bipolar/BiCMOS Circuits and Technology Meeting, 2005. Proceedings of the; 11/2005
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C. Bernier,
F. Hameau, G. Billiot,
E. de Foucauld,
S. Robinet,
J. Durupt,
F. Dehmas,
E. Mercier,
P. Vincent,
L. Ouvry,
D. Lattard,
M. Gary,
C. Bour,
J. Prouvee,
S. Dumas
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ABSTRACT: A fully integrated 2.4 GHz transceiver based on the IEEE802.15.4 specification has been designed using a 130 nm CMOS technology. Concurrent system and design optimizations were required to reach an energy efficiency of 21.5 nJ/bit in RX mode and 32.5 nJ/bit in TX modes, respectively, at a data rate of 250 kbit/s. The circuit includes a -5 dBm transmitter, a -81 dBm sensitivity receiver, an integer N PLL with 5 MHz reference, a dual I/Q 3-bit ADC at 4 MS/s, an analog RSSI with 8-bit ADC at 8 kS/s and an integrated SPDT TX/RX switch to a 100 Omega differential antenna port. The chip consumes 5.4 mW in RX mode and 8.1 mW in TX mode under 1.2 V.
Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE;
