A. Mariano

Universidade Federal do Paraná, Pontal do Paraná, Paraná, Brazil

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Publications (20)1.11 Total impact

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    ABSTRACT: This paper presents an ultra low power consumption 65 GHz LC-VCO dedicated to wireless high data rate applications. It is designed in a 65 nm CMOS SOI process, which improves passive devices behavior. The proposed VCO achieves a frequency tuning range (FTR) of 9.7 % and a phase noise of −110.86 dBc/Hz at 10 MHz of the carrier. All integrated passive components (including transmission lines and a transformer-based balun) are modeled using advanced electromagnetic (EM) field solvers. The power consumption of the proposed VCO is as low as 1.1 mW when biased by a 0.8-V supply voltage. The FoM of this millimeter wave circuit, whose core occupies a silicon footprint of only 0.047 mm2, is −184.07 dBc/Hz.
    Analog Integrated Circuits and Signal Processing 09/2013; · 0.55 Impact Factor
  • A. Mariano, F. Rivet
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    ABSTRACT: Modern electronic systems claim for Analog-to-Digital (A/D) interfaces with strong requirements in terms of resolution and frequency. Among several A/D architectures that intent to achieve these hard specifications, Time-Interleaved Analog-to-Digital Converters (TIADC) arises as a competitive candidate. TIADC offer a higher sampling frequency with suitable moderate power consumption. However, their architecture introduces mismatch errors that affect the resolution of data conversion. Calibration methods permit to reduce significantly the impact of these errors. A possible solution is the insertion of an additional circuitry in the A/D conversion system: a Built-In Self-Calibration (BISC). A BISC system aims to compensate imperfections from the TIADC, such as offset, gain and timing errors. Despite the benefits carried by the BISC, this system also introduces errors in the overall data conversion system. This paper proposes a case study of a mixed-signal BISC TIADC, highlighting the strengths and the weakness of using built-in calibration circuits. Supplementary calibration methods will be explored to mitigate the impact of the BISC and to improve the A/D conversion performance. The debate is open: how calibration systems must be calibrated?
    New Circuits and Systems Conference (NEWCAS), 2012 IEEE 10th International; 01/2012
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    ABSTRACT: This paper presents a 65 GHz LC-VCO dedicated to wireless high data rate applications. It is designed in a 65nm CMOS SOI process. The proposed VCO achieves a frequency tuning range (FTR) of some 9.7% and a phase noise of −111 dBc/Hz at 10 MHz of the carrier. The power consumption is 1.1 mW when biased with a 0.8 V power supply. The silicon footprint of the VCO core is only 0.047 mm2.
    01/2012;
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    ABSTRACT: Radiofrequency (RF) energy harvesting is a key technique that can be employed in systems for generating some amount of electrical power to drive circuits in wireless communicating devices or, even so, to power supply a full node in wireless sensor networks (WSNs). This paper presents the comparison between two different CMOS rectifier topologies operating in the 900 MHz and 2.4 GHz ISM bands to convert RF power into DC power, both implemented in a CMOS 130nm technology. The first one is a traditional voltage multiplier today commonly used for scavenging energy from RF sources and for RFID applications. The second one is a cross-coupled voltage multiplier, which achieves a significant improvement in power efficiency and low voltage-drop compared with the traditional circuit.
    Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on; 01/2012
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    ABSTRACT: A millimeter-wave (mmW) chipset for 77-81 GHz automotive radar has been developed in 0.13μm SiGe HBT technology. This work presents the performances of an integrated Low Noise Amplifier (LNA), a Power Amplifier (PA), a down-converting Mixer, and also a Voltage Controlled Oscillator (VCO). For successful implementation of the circuit, considerations on the reliability of the design have been taken into account. Measurements on all circuits confirm the feasibility of mmW front-end using silicon based technologies for W-band application.
    New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International; 07/2011
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    ABSTRACT: A fourth-order bandpass Delta-Sigma converter with integrated LC resonators is presented in this paper. It is based on a multi-feedback architecture with a multi-bit quantizer in the main modulator path. This architecture allows achieving high-order noise-shaping maintaining modulator stability. Two integrated LC resonators with active Q-enhancement circuits are used in order to improve the overall resonator quality factor. This data converter is designed in a 0.13 μm CMOS process from STMicroelectronics. It achieves a DR of 68 dB in 30 MHz bandwidth with a 4 GHz sampling frequency.
    Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on; 01/2011
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    ABSTRACT: A 79GHz receiver front-end for automotive applications has been implemented in a 130nm SiGe technology supporting millimeter wave design. The receiver consists of a two-stage LNA, a double-balanced down-conversion Mixer and a synchronized VCO. Design and test results for each RF circuit block are presented, followed by a characterization of the integrated receiver.
    Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2011 IEEE; 01/2011
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    ABSTRACT: In this paper, we present a mixer implemented in a 130 nm BiCMOS technology dedicated to 77 GHz automotive radar applications. The architecture is based on a double-balanced Gilbert cell with integrated transformer-based Baluns. Interconnections between devices, capacitor accesses and Tee-junctions are modeled using EM software in order to improve the simulation accuracy. The measurement results of the circuit exhibit a conversion gain and a SSB noise figure of 18.5 dB and 13.8 dB respectively over a 74 to 81 GHz band. Supplied under 2.5 V the power consumption is 80 mW and the ICP1 is -13 dBm. The transformer-based Balun allows a good input matching at the RF input port over a 16 GHz range from 72 to 88 GHz.
    ESSCIRC, 2010 Proceedings of the; 10/2010
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    ABSTRACT: In this paper, we present a low power and high gain mixer dedicated to 77 GHz automotive radar applications. The architecture is based on a double-balanced active Gilbert cell with integrated transformer-based Baluns. These Baluns allow converting the single-ended input signals to differential with an amplitude and phase imbalance of 0.3 dB and 179°, respectively. Interconnections between devices, capacitor accesses and Tee-junctions are modeled using HFSS simulator in order to improve the simulation accuracy. The proposed mixer consumes 105 mW and achieves 16.4 dB of conversion gain and 13.2 dB of noise figure.
    NEWCAS Conference (NEWCAS), 2010 8th IEEE International; 07/2010
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    ABSTRACT: Analog-to-Digital (A/D) conversion is faced with strong requirements in terms of resolution and frequency. Time-Interleaved Analog-to-Digital Converters (TIADC) are popular because they offer a higher sampling frequency. But, their architecture introduces errors that affect the resolution of conversion. This paper presents a built-in method of calibration dedicated to TIADC. Mixed-simulations are performed merging transistor-level in 65nm CMOS technology and behavioral blocks in VHDL-AMS language to validate the feasibility of a Built-In Self-Calibration (BISC) system which corrects offset, gain and timing error. Technological constraints of the analog part of the BISC circuitry are highlighted. An orthogonal calibration is applied in a 4-ADC TIADC system and a detailed choice of the methodology is described.
    NEWCAS Conference (NEWCAS), 2010 8th IEEE International; 07/2010
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    ABSTRACT: This paper presents a comparative study between two mm-wave technologies from STMicroelectronics: 130 nm BiCMOS and 65 nm CMOS-SOI, through the implementation of a single stage LNA at 60 GHz. Both distributed and lumped design approaches are investigated to work out the best trade-off between silicon saving and performances. The two circuits achieve respectively 12 dB and 6 dB gain, 3.6 dB and 4.5 dB noise figure under 2.5V and 1.2V supply voltage for BiCMOS9MW and CMOS-SOI technologies. The LNA are based on cascode topology with a specific interstage matching for f<sub>t</sub> and f<sub>max</sub> improvement. The current density and transistor sizing are set to perform the lowest NF at 60 GHz, the current consumption is 3.7 mA and 13 mA for BiCMOS9MW and CMOS-SOI LNA respectively.
    Signals, Circuits and Systems (SCS), 2009 3rd International Conference on; 12/2009
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    ABSTRACT: Transistor-level simulation of complex systems involving analog and digital parts is a time-consuming task. The growing interaction of analog and digital devices calls for the use of top-down design methodologies, resulting in behavioral modeling at different levels of abstraction. In this article, an advanced design methodology using a combination of behavioral models and transistor-level models is presented. This methodology is very interesting for complex mixed-signal IC design, improving the design flexibility and reducing the simulation time. To validate the proposed methodology, a continuous-time delta–sigma modulator based on a high-speed low-resolution quantizer is modeled, taking into account their nonidealities such as excess loop delay, clock jitter and feedback DAC element mismatch. The main features of the multi-bit quantizer are 3-bit resolution with 4GHz sampling rate and FOM of about 7pJ/conv. This modulator samples signals at high-IF, performing directly the analog-to-digital conversion in the modern RF front-end receivers.
    Analog Integrated Circuits and Signal Processing 08/2009; 60(1):145-153. · 0.55 Impact Factor
  • J.B. Begueret, A. Mariano, D. Dallet
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    ABSTRACT: This paper deals with general discussion over high-speed data converter architectures. Nowadays, more and more researches are focused on the ability to design transceivers able to manage digital data as soon as possible right behind the antenna. These so-called Software Defined Radio architectures are one of the easiest ways to design a receiver with low time-to-market impact. Furthermore, most of the recent standards impose either very high frequency ranges, large bandwidth signals and numerous number of bits. Indeed, different topologies of analog-to-digital and digital-to-analog converters are discussed, keeping in mind the very high frequency purpose. To conclude this paper, two designs are presented: a wideband 3-bit 4 Gsps Flash converter and a narrowband 12-bit 4 Gsps Continuous Time Delta-Sigma converter.
    Bipolar/BiCMOS Circuits and Technology Meeting, 2008. BCTM 2008. IEEE; 11/2008
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    ABSTRACT: This paper presents an advanced design methodology using a combination of behavioral models and transistor level models. This methodology is very interesting for complex mixed-signal IC design, improving the design flexibility and reducing the simulation time. In order to validate the proposed methodology, a continuous-time delta-sigma modulator based on a high-speed low-resolution analog-to-digital converter is modeled. This modulator samples at high-IF signals, performing the direct conversion in the modern RF front-end receivers.
    Circuits and Systems, 2007. NEWCAS 2007. IEEE Northeast Workshop on; 09/2007
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    ABSTRACT: A High-Speed Multi-Bit Bandpass Continuous- Time Delta-Sigma Modulator is presented in this paper. This modulator samples at high-IF signals, performing the direct conversion in the modern RF front-end receivers. In order to improve the design flexibility, an advanced design methodology is used. This methodology is very interesting for complex mixed-signal IC design, since it combines behavioral models and transistor level models in the same environment, reducing the simulation time.
    Research in Microelectronics and Electronics Conference, 2007. PRIME 2007. Ph.D.; 08/2007
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    ABSTRACT: Modern front-end receivers perform direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The final aspiration is to directly digitize the RF signal and hence eliminate any RF/analog mixers. In order to direct digitize the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these specifications, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) to be used as a quantizer in modern digital receivers. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sample rate in a 0.8-2GHz bandwidth.
    Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007; 01/2007
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    ABSTRACT: We present in this article a fourth-order integrated LC bandpass Delta-Sigma modulator for direct conversion of high intermediate frequencies. It is designed in a 0.25 μm BiCMOS SiGe:C process from STMicroelectronics. The modulator is able to direct digitize a 1GHz IF signal in a 20MHz bandwidth. The continuous-time loop filter employs two integrated LC resonators with active Q?enhancement circuits. A multi-feedback architecture is used to achieve higher order noise-shaping, while maintaining the modulator stability. A multibit quantizer was implemented to reduce quantization noise and improve stability.
    Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006; 01/2006
  • A. A. Mariano, D. Dallet, Y. Deval, J.-B. Begueret
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    ABSTRACT: A fourth-order integrated LC bandpass delta-sigma modulator is presented. It is designed in a 0.25 mum BiCMOS SiGe:C process from STMicroelectronics. The modulator can directly digitize high intermediate signals in a 20MHz bandwidth. It employs two integrated LC resonators with active Q-enhancement circuits. A multi-feedback architecture is used to achieve higher order noise-shaping, while maintaining the modulator stability. A multibit quantizer was implemented to reduce quantization noise and improve stability
    01/2006;
  • Source
    A. Mariano, D. Dallet, Y. Deval
  • Source
    A. Mariano, D. Dallet, Y. Deval
    [Show abstract] [Hide abstract]
    ABSTRACT: An advanced design methodology using a combination of behavioral models and transistor level models is presented in this paper. This methodology is very interesting for complex mixed-signal IC design, reducing the simulation time and improving the design flexibility. In order to validate the methodology proposed, a High-Speed Bandpass Continuous-Time Delta-Sigma Modulator is modeled. This modulator samples at high-IF signals, performing the direct conversion in the modern RF front- end receivers.