Edoardo Bonizzoni

University of Pavia, Ticinum, Lombardy, Italy

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Publications (85)14.52 Total impact

  • Analog Integrated Circuits and Signal Processing 01/2015; DOI:10.1007/s10470-015-0492-4 · 0.40 Impact Factor
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    ABSTRACT: This paper presents a four-folded current-mode vertical Hall device. The current spinning technique is applied to a vertical Hall sensor driven in current mode to eliminate the offset and to increase the sensitivity. Different geometries have been studied and simulated by using a simulator based on finite element method. A four-folded three contacts vertical Hall device model displayed the lowest residual offset and the best sensitivity. Simulations results, obtained in two different environments, are compared and discussed. COMSOL results are validated with respect to the electrical behavior of an 8-resistor Verilog-A model implemented in Cadence environment. Simulations show that the achieved sensitivity can be better than 160 mT-1, a remarkable performance for vertical Hall sensors.
    2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME); 06/2014
  • Da Feng, Sai-Weng Sin, Edoardo Bonizzoni, Franco Maloberti
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    ABSTRACT: A four-path time interleaved current steering DAC is presented. It requires the same number of unity current generators of the plain counterpart, thanks to the use of a digital ΣΔ modulator, thus leading to a lower number of unity current switchings. The benefit is that the non-linearity caused by clock feedthrough is attenuated. Behavioral level simulation results show that the SFDR of a 12-bit DAC operating at 12 GS/s can be 60 dB.
    2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME); 06/2014
  • Yao Liu, Edoardo Bonizzoni, Franco Maloberti
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    ABSTRACT: This paper describes a multi-bit third-order incremental analog-to-digital (ADC) architecture and design considerations to achieve 18-bit resolution. The architecture uses multi-bit quantization in order to increase resolution and reduce the output swing of op-amps. The non-linearity due to the mismatch of unity elements of multi-bit DAC is properly compensated for with Smart-DEM algorithm. This 2+1 incremental architecture achieves 18-bit resolution with a 3-bit quantizer. Simulation results verify the target resolution achieved with 61 clock periods despite a large unity element mismatch (3σ = 0.5%).
    2014 IEEE International Symposium on Circuits and Systems (ISCAS); 06/2014
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    ABSTRACT: A magnetic Hall sensor working in the current-mode is presented. The proposed sensing device is composed by two Hall plates able to provide a differential current at the output nodes. The sensor, fabricated in a standard 0.18-μm CMOS technology, uses the spinning-current technique to compensate for the offset and obtains a sensitivity IHall/(B⊥Ibias) better than 0.02 T-1 for magnetic fields ranging from 0 to 10 mT.
    2014 IEEE International Symposium on Circuits and Systems (ISCAS); 06/2014
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    ABSTRACT: This paper proposes the use of sampled-data operation in op-amps. The technique favors very low supply voltage and micro-power. After discussing the method at a general level, a possible sampled-data scheme is analyzed. Simulations with a low threshold technology show that a 0.5-V supply is possible. A version of the circuit, which has been integrated by using a standard 0.18-μm CMOS technology (with high thresholds), is able to operate at 0.65-V supply voltage. Simulation results show 42.5 dB of DC gain and 2.5-kHz bandwidth with 0.5-pF load capacitor. The power consumption is 63 nW. A pseudo-differential scheme doubles the consumed power and increases the DC gain by 6 dB.
    2014 IEEE International Symposium on Circuits and Systems (ISCAS); 06/2014
  • Yao Liu, E. Bonizzoni, A. D'Amato, F. Maloberti
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    ABSTRACT: This paper presents a second-order 3-bit incremental converter, which uses a novel Smart-DEM algorithm for mismatch compensation of multi-level DAC unity elements. The circuit, fabricated in a mixed 0.18-0.5-μm CMOS technology, achieves more than 17-bit resolution over a 5-kHz bandwidth using 256 clock periods. A single-step chopping of the input stage leads to a residual offset of 9.7 μV. The measured SFDR and power consumption are -90 dB and 280 μW, respectively. The achieved Figure of Merit is 177.5 dB.
    ESSCIRC (ESSCIRC), 2013 Proceedings of the; 01/2013
  • H. Heidari, U. Gatti, E. Bonizzoni, F. Maloberti
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    ABSTRACT: The performances of a current-mode Hall sensor featuring output current signals are discussed. The current-mode approach is analyzed by applying for first time to our best knowledge the spinning current technique to Hall plate working in current-mode to eliminate offset and 1/f noise. Among different geometries that have been studied and simulated using COMSOL MultiphysicsTM, cross-shaped model displayed the lowest noise and residual offset and the best sensitivity. The COMSOL results determined a behavioral model implemented in Verilog-A for simulations in the Cadence environment. Simulations results achieved in COMSOL and in Cadence environment show the potentiality, thus demonstrating the effectiveness of the approach, for a possible use of the device with remarkable performances.
    Ph.D. Research in Microelectronics and Electronics (PRIME), 2013 9th Conference on; 01/2013
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    ABSTRACT: This paper presents a two-path design of quadrature band-pass ΣΔ modulators and discusses the architectural level implementation issues for power reduction. The methodology uses an architecture which locks IF frequencies to the sampling frequency. The basic delay based solution is converted into integrator based solution for the implementation. Robustness of the structure against the mismatch is analyzed and a two-path quadrature cascaded modulator is proposed to alleviate signal band gain error tone. Simulations at the behavioral level verify the architecture implementation and the effectiveness of the approach.
    VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on; 01/2013
  • O. Belotti, E. Bonizzoni, F. Maloberti
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    ABSTRACT: This paper presents the design of a third-order ΣΔ modulator targeted for WCDMA applications. The architecture uses two operational amplifiers and distributed fully digital feed-forward paths to minimize the output swing of op-amps. Simulation results show that first and second integrator output swings are reduced by 88% and 75%, respectively. Post-layout simulation results of the modulator, designed in 65-nm CMOS technology, give a SNDR of 83 dB over a signal bandwidth of 2.2 MHz. The power consumption is 2.3 mW and the achieved FoM is equal to 172.8 dB.
    Circuits and Systems (ISCAS), 2013 IEEE International Symposium on; 01/2013
  • Yao Liu, E. Bonizzoni, F. Maloberti
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    ABSTRACT: This paper describes the design method for highorder multi-bit incremental converters aiming at high resolution (> 14 bits) with Smart-DEM algorithm. Traditional 2nd and 3rd-order incremental ADCs use 1-bit quantizer. These structures lead to long conversion time for each sample to achieve the expected resolution and high power consumption due to the large output swing of the op-amps. Also, the fractional coefficients along the accumulation path that avoid instability degrade the performance. On the contrary, modulators employing multi-bit quantizer and DAC do not suffer from these problems. Although the mismatch of unity elements in the DAC causes non-linearity issue, this can be suppressed by Smart-DEM algorithm. Because the Smart-DEM algorithm is quite compact and easy to implement, the modulator benefits extra bits performance directly from the multi-bit DAC with affordable digital circuits overhead. In this paper several structures for incremental ADCs utilizing multi-bit quantizer are presented. The positive-and-negative DAC and the Smart-DEM algorithm are explained. With 3-bit quantizer, the simulation results show that the 2nd-order incremental ADC obtains 18-bit resolution with 256 clock periods.
    Circuits and Systems (ISCAS), 2013 IEEE International Symposium on; 01/2013
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    ABSTRACT: This paper presents design and experimental results of a second-order, discrete-time, quadrature band-pass ΣΔ modulator targeted for wireless body area networks. The non-conventional architecture locks the intermediate frequency (IF) to the sampling frequency. Measurement results collected from a CMOS 0.18-μm prototype achieves a peak SNR of 55 dB over 100-kHz bandwidth and 40-dB SNR over 2.6-MHz bandwidth for a sampling frequency of 20 MHz with 1.96 mW power dissipation.
    Circuits and Systems (ISCAS), 2013 IEEE International Symposium on; 01/2013
  • Oscar Belotti, Edoardo Bonizzoni, Franco Maloberti
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    ABSTRACT: A technique for the exact design of the noise transfer function of Continuous-Time (CT) Sigma-Delta modulators with arbitrary and multiple DAC responses and real op-amps is here presented. The approach, that presupposes linear behavior of active blocks, produces a CT modulator with the same noise shaping as its Discrete-Time counterpart. The method operates entirely in the time domain and accounts for non-idealities of real implementations such as finite gain and bandwidth of integrators. The procedure can be effectively implemented with circuit simulators to allow the exact design with transistor level blocks. A design example on a third-order scheme confirms the effectiveness of the method.
    Analog Integrated Circuits and Signal Processing 10/2012; 73(1). DOI:10.1007/s10470-012-9866-z · 0.40 Impact Factor
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    ABSTRACT: A MASH bandpass $\Upsigma\Updelta$ modulator for wide-band code division multiple access (WCDMA) applications is presented. The signal bandwidth of the proposed modulator is 10 MHz centered around an intermediate frequency (IF) of 70.5 MHz. Two two-path second-order bandpass $\Upsigma\Updelta$ modulators make the MASH architecture, which realizes a noise transfer function with four couples of complex conjugate zeros. The proposed circuit, fabricated with a 0.18 μm CMOS technology, uses a sampling frequency of 180 MHz to obtain a resolution of about 12 bits in the 10 MHz bandwidth around the IF. The measured modulator power consumption is 95 mW with a supply voltage of 1.8 V. The achieved figure-of-merit (FoM BP ) is 0.37 pJ/conversion-level.
    Analog Integrated Circuits and Signal Processing 06/2012; 71(3). DOI:10.1007/s10470-011-9795-2 · 0.40 Impact Factor
  • O. Belotti, E. Bonizzoni, F. Maloberti
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    ABSTRACT: A second-order multi-bit hybrid continuous-time (CT) ΣΔ modulator has been implemented in a 65-nm CMOS technology. The circuit ensures jitter immunity granted by the use of multi-rate switched-capacitor (SC) DACs. An auxiliary digital assistance technique reduces integrators output swing. The modulator provides 10.8 bits of resolution over a signal bandwidth of 1.1 MHz and a spurious free dynamic range (SFDR) of 78 dB. The chip draws 1.1 mW from a 1-V supply.
    Circuits and Systems (ISCAS), 2012 IEEE International Symposium on; 01/2012
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    ABSTRACT: An incremental ADC for Wheatstone CMOS stress sensor systems is described. A switched-capacitors integrator without switches toward virtual ground avoids spur signals, clock feed-through, residual offset and glitches. The circuit, fabricated in a 0.35-μm CMOS technology, consumes 42 μW at 500-kHz clock and 2.8-V supply. Low speed chopping cancels offset and limits the 1/f noise contribution. The signal-to-noise ratio with measures lasting 220 periods is 114 dB at ±100 mV full-scale range. The active area is 0.32 mm2.
    ESSCIRC (ESSCIRC), 2012 Proceedings of the; 01/2012
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    ABSTRACT: This paper presents a new concept for an effective design of quadrature band-pass ΣΔ modulators with built-in Signal Transfer Function (STF) filtering action and discusses the architectural level implementation issues for second and third order modulators based on delay line topologies. The methodology uses an architecture which locks the intermediate frequency (IF) to the sampling frequency for both STF and Noise Transfer Function (NTF). Robustness of the structure against the mismatch is analyzed with interference tones placed in different locations of the receiver spectrum, including the image band. Simulations at the behavioral level verify the architecture implementation and the effectiveness of the approach.
    Circuits and Systems (ISCAS), 2012 IEEE International Symposium on; 01/2012
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    ABSTRACT: A design technique for a double-delay based quadrature ΣΔ modulator is presented. The architecture uses a two-path scheme, which avoids mirror tones in the signal band and locks the intermediate frequency with the clock, thus avoiding the trimming requirement. The two-path architecture and time interleaving lead to an overall power reduction by a factor of 8.
    Electronics Letters 11/2011; 47(24):1316-1317. DOI:10.1049/el.2011.2532 · 1.07 Impact Factor
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    Yao Liu, E. Bonizzoni, F. Maloberti
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    ABSTRACT: The concept of high-order ramp analog-to-digital converter and its design aiming at medium-high resolution (12-14 bits) are presented. Design methods that give rise to various Nyquist rate schemes resembling incremental converters are described. Since for Nyquist rate achieving noise shaping is not the goal, the design care is just maintaining good stability to avoid performance degradation. Different architectures for second and third-order ramp converters are presented and verified at the behavioral level. Simulation results show how the use of extra quantizers and multi-bit resolutions reduces integrators output swing and enhances overall performance. Finally, possible digital assistance actions are presented and discussed.
    Circuit Theory and Design (ECCTD), 2011 20th European Conference on; 10/2011
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    Andrea Agnes, Edoardo Bonizzoni, Franco Maloberti
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    ABSTRACT: This paper describes an incremental converter based on a second order ΣΔ modulator. The scheme uses a 3-bit DAC with inherent linearity, an optimal reset of integrators, and gives rise to an effective offset cancellation with a novel technique based on single or double chopping. The circuit, fabricated in a mixed 0.18-0.6 μm CMOS technology, obtains 1.5-μV residual offset with 2VPP fully differential range. The measured resolution is 19 bit obtained with 512 clock periods.
    Analog Integrated Circuits and Signal Processing 09/2011; 72(3). DOI:10.1007/s10470-011-9752-0 · 0.40 Impact Factor