E. Bonizzoni

University of Pavia, Ticinum, Lombardy, Italy

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Publications (78)14.1 Total impact

  • H. Heidari, U. Gatti, E. Bonizzoni, F. Maloberti
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    ABSTRACT: The performances of a current-mode Hall sensor featuring output current signals are discussed. The current-mode approach is analyzed by applying for first time to our best knowledge the spinning current technique to Hall plate working in current-mode to eliminate offset and 1/f noise. Among different geometries that have been studied and simulated using COMSOL MultiphysicsTM, cross-shaped model displayed the lowest noise and residual offset and the best sensitivity. The COMSOL results determined a behavioral model implemented in Verilog-A for simulations in the Cadence environment. Simulations results achieved in COMSOL and in Cadence environment show the potentiality, thus demonstrating the effectiveness of the approach, for a possible use of the device with remarkable performances.
    Ph.D. Research in Microelectronics and Electronics (PRIME), 2013 9th Conference on; 01/2013
  • Yao Liu, E. Bonizzoni, A. D'Amato, F. Maloberti
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    ABSTRACT: This paper presents a second-order 3-bit incremental converter, which uses a novel Smart-DEM algorithm for mismatch compensation of multi-level DAC unity elements. The circuit, fabricated in a mixed 0.18-0.5-μm CMOS technology, achieves more than 17-bit resolution over a 5-kHz bandwidth using 256 clock periods. A single-step chopping of the input stage leads to a residual offset of 9.7 μV. The measured SFDR and power consumption are -90 dB and 280 μW, respectively. The achieved Figure of Merit is 177.5 dB.
    ESSCIRC (ESSCIRC), 2013 Proceedings of the; 01/2013
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    ABSTRACT: This paper presents design and experimental results of a second-order, discrete-time, quadrature band-pass ΣΔ modulator targeted for wireless body area networks. The non-conventional architecture locks the intermediate frequency (IF) to the sampling frequency. Measurement results collected from a CMOS 0.18-μm prototype achieves a peak SNR of 55 dB over 100-kHz bandwidth and 40-dB SNR over 2.6-MHz bandwidth for a sampling frequency of 20 MHz with 1.96 mW power dissipation.
    Circuits and Systems (ISCAS), 2013 IEEE International Symposium on; 01/2013
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    ABSTRACT: This paper presents a two-path design of quadrature band-pass ΣΔ modulators and discusses the architectural level implementation issues for power reduction. The methodology uses an architecture which locks IF frequencies to the sampling frequency. The basic delay based solution is converted into integrator based solution for the implementation. Robustness of the structure against the mismatch is analyzed and a two-path quadrature cascaded modulator is proposed to alleviate signal band gain error tone. Simulations at the behavioral level verify the architecture implementation and the effectiveness of the approach.
    VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013 26th International Conference on; 01/2013
  • O. Belotti, E. Bonizzoni, F. Maloberti
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    ABSTRACT: This paper presents the design of a third-order ΣΔ modulator targeted for WCDMA applications. The architecture uses two operational amplifiers and distributed fully digital feed-forward paths to minimize the output swing of op-amps. Simulation results show that first and second integrator output swings are reduced by 88% and 75%, respectively. Post-layout simulation results of the modulator, designed in 65-nm CMOS technology, give a SNDR of 83 dB over a signal bandwidth of 2.2 MHz. The power consumption is 2.3 mW and the achieved FoM is equal to 172.8 dB.
    Circuits and Systems (ISCAS), 2013 IEEE International Symposium on; 01/2013
  • Yao Liu, E. Bonizzoni, F. Maloberti
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    ABSTRACT: This paper describes the design method for highorder multi-bit incremental converters aiming at high resolution (> 14 bits) with Smart-DEM algorithm. Traditional 2nd and 3rd-order incremental ADCs use 1-bit quantizer. These structures lead to long conversion time for each sample to achieve the expected resolution and high power consumption due to the large output swing of the op-amps. Also, the fractional coefficients along the accumulation path that avoid instability degrade the performance. On the contrary, modulators employing multi-bit quantizer and DAC do not suffer from these problems. Although the mismatch of unity elements in the DAC causes non-linearity issue, this can be suppressed by Smart-DEM algorithm. Because the Smart-DEM algorithm is quite compact and easy to implement, the modulator benefits extra bits performance directly from the multi-bit DAC with affordable digital circuits overhead. In this paper several structures for incremental ADCs utilizing multi-bit quantizer are presented. The positive-and-negative DAC and the Smart-DEM algorithm are explained. With 3-bit quantizer, the simulation results show that the 2nd-order incremental ADC obtains 18-bit resolution with 256 clock periods.
    Circuits and Systems (ISCAS), 2013 IEEE International Symposium on; 01/2013
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    ABSTRACT: An incremental ADC for Wheatstone CMOS stress sensor systems is described. A switched-capacitors integrator without switches toward virtual ground avoids spur signals, clock feed-through, residual offset and glitches. The circuit, fabricated in a 0.35-μm CMOS technology, consumes 42 μW at 500-kHz clock and 2.8-V supply. Low speed chopping cancels offset and limits the 1/f noise contribution. The signal-to-noise ratio with measures lasting 220 periods is 114 dB at ±100 mV full-scale range. The active area is 0.32 mm2.
    ESSCIRC (ESSCIRC), 2012 Proceedings of the; 01/2012
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    ABSTRACT: This paper presents a new concept for an effective design of quadrature band-pass ΣΔ modulators with built-in Signal Transfer Function (STF) filtering action and discusses the architectural level implementation issues for second and third order modulators based on delay line topologies. The methodology uses an architecture which locks the intermediate frequency (IF) to the sampling frequency for both STF and Noise Transfer Function (NTF). Robustness of the structure against the mismatch is analyzed with interference tones placed in different locations of the receiver spectrum, including the image band. Simulations at the behavioral level verify the architecture implementation and the effectiveness of the approach.
    Circuits and Systems (ISCAS), 2012 IEEE International Symposium on; 01/2012
  • O. Belotti, E. Bonizzoni, F. Maloberti
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    ABSTRACT: A second-order multi-bit hybrid continuous-time (CT) ΣΔ modulator has been implemented in a 65-nm CMOS technology. The circuit ensures jitter immunity granted by the use of multi-rate switched-capacitor (SC) DACs. An auxiliary digital assistance technique reduces integrators output swing. The modulator provides 10.8 bits of resolution over a signal bandwidth of 1.1 MHz and a spurious free dynamic range (SFDR) of 78 dB. The chip draws 1.1 mW from a 1-V supply.
    Circuits and Systems (ISCAS), 2012 IEEE International Symposium on; 01/2012
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    Yao Liu, E. Bonizzoni, F. Maloberti
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    ABSTRACT: The concept of high-order ramp analog-to-digital converter and its design aiming at medium-high resolution (12-14 bits) are presented. Design methods that give rise to various Nyquist rate schemes resembling incremental converters are described. Since for Nyquist rate achieving noise shaping is not the goal, the design care is just maintaining good stability to avoid performance degradation. Different architectures for second and third-order ramp converters are presented and verified at the behavioral level. Simulation results show how the use of extra quantizers and multi-bit resolutions reduces integrators output swing and enhances overall performance. Finally, possible digital assistance actions are presented and discussed.
    Circuit Theory and Design (ECCTD), 2011 20th European Conference on; 10/2011
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    A.P. Perez, E. Bonizzoni, F. Maloberti
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    ABSTRACT: This third-order ΔΣ modulator, suitable for high-resolution low-power sensor systems, consumes 140μW to obtain 84dB SNDR with OSR=16 and 100kHz signal bandwidth. The achieved FoM is 54fJ/conversion-step. The DACs use a single resistive divider to generate 32 differential 5b reference voltages. The proposed scheme totally cancels the error caused by gradient in the resistance values. Resistor sizes and layout of the resistive DAC limit the high-order distortion terms and obtain an SFDR of 96dB at -4dB<sub>FS</sub> without the need for digital calibration or dynamic element matching (DEM).
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International; 03/2011
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    ABSTRACT: This paper presents a third-order Sigma-Delta modulator that uses only two operational amplifiers. A fully digital solution reduces both amplifiers output swings. This design achieves complex conjugate zeros that allows obtaining a signal-to-noise ratio of about 8 dB better than having all the zeros placed at z = 1. Behavioral level simulations demonstrate the effectiveness of the approach.
    Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on; 01/2011
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    ABSTRACT: A low-power spur-free precision amplifier, which uses input chopping and correlated double sampling for demodulation, is presented. This circuit employs an AC coupling between the first and the second stage that removes the first stage offset without causing ripple. The input rail-to-rail circuit, fabricated in a mixed 0.18-0.5 μm CMOS technology, operates with supply ranging from 1.8 V to 5 V. The circuit achieves a simulated 168-dB DC gain with an overall current consumption of 14.4 μA. The measured offset voltage over the available samples results in a distribution with 2-μV standard deviation. The obtained input noise density at low-frequency equal to 37 nV/√Hz gives a 5.5 noise efficiency factor.
    IEEE Journal of Solid-State Circuits 01/2011; · 3.06 Impact Factor
  • Oscar Belotti, Edoardo Bonizzoni, Franco Maloberti
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    ABSTRACT: Methods for avoiding the slew-rate limit and the optimal design of hybrid Continuous-Time (CT) modulators with switched-capacitor (SC) DAC are discussed. Limitations on performance due to finite bandwidth and slew-rate of the opera- tional amplifier are analyzed. The use of multi-rate scheme made by a set of time-interleaved SC-DAC moderates the non-linear error caused by the limited slew-rate in mono-rate converter at equal slew-rate. Behavioral level simulations confirm the validity of proposed technique.
    01/2011;
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    Yao Liu, Edoardo Bonizzoni, Franco Maloberti
    20th European Conference on Circuit Theory and Design, ECCTD 2011, Linkoping, Sweden, Aug. 29-31, 2011; 01/2011
  • Aldo Pena-Perez, Edoardo Bonizzoni, Franco Maloberti
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    ABSTRACT: sonable value. The solution also allows the use of 5b flash converter, an impractical value for digital calibration or DEM techniques. The expected matching is 0.1%, leading to harmonic distortion of more than 86dB without any calibration. Three intermediate taps on the resistive string connected to output pins allow us to measure the gradient in the poly resistor values. Figure 27.5.4 shows the schematic of the operational amplifier. It is a conventional two-stage amplifier with 65dB of gain and 60μW of total power consumption. It has a simulated bandwidth of 25MHz with 67° of phase margin. The 3.2MHz clock frequency and the multiplexed operation require a slew-rate much higher than what such op-amp can provide. The use of the slew-rate booster shown in the top section of the schematic solves this problem at the cost of an extra current of 10μA (25% of the op-amp bias). The bias current of the differential pair established by VBB is 10μA. The bias of the PMOS loads in the slewrate booster circuit gives rise to 7μA in saturation. Thus, with balanced inputs, the current in the diode-connected transistors MM5 and MM6 is zero. Slewing directs all the 10μA in one branch and one of the diode-connected transistors drains 3μA. This current and its mirrored version multiplied by suitable factors augments the slewing currents of the main amplifier. The slew rate goes from 4 to 15.5V/μsec.
    IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011; 01/2011
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    ABSTRACT: A design technique for a double-delay based quadrature ΣΔ modulator is presented. The architecture uses a two-path scheme, which avoids mirror tones in the signal band and locks the intermediate frequency with the clock, thus avoiding the trimming requirement. The two-path architecture and time interleaving lead to an overall power reduction by a factor of 8.
    Electronics Letters 01/2011; 47(24):1316-1317. · 1.04 Impact Factor
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    ABSTRACT: This paper presents a single-inductor 4-outputs DC–DC buck converter. In order to independently regulate the four output voltages, a multiple control loop operates on linear combinations of the output voltage errors. An original self-boosted snubber circuit enables load power switches control signals boosting without area and power efficiency penalties. The circuit, fabricated using a 0.5-μm CMOS process, provides four output voltages that can be independently regulated from 0V to the used supply voltage −500mV. The supply voltage can range from 2.3 up to 5V. The overall minimum and maximum output currents are 0.15 and 1.8A, respectively. The measured maximum cross regulation is 40mV/V with a peak of power efficiency equal to 85%. KeywordsDC–DC converters–Buck converter–Single-inductor multiple-output
    Analog Integrated Circuits and Signal Processing 01/2011; 67(2):169-177. · 0.55 Impact Factor
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    Aldo Pena-Perez, Edoardo Bonizzoni, Franco Maloberti
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    ABSTRACT: An architecture for low-power modulators suit- able for high-resolution portable sensor systems is presented. The circuit uses a single operational amplifier to achieve a third- order noise shaping. The two-stage op-amp employs a boosting technique that increases by 5 the slew-rate. The circuit, simulated at the transistor level using a conventional 0.18-m CMOS technology, obtains a peak SNDR of 88 dB over an input signal bandwidth of 100 kHz. The simulated power consumption is 125 W with a 1.5-V supply voltage. The achieved Figure of Merit (FoM) is 31 fJ/conversion-level.
    International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil; 01/2011
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    ABSTRACT: In this paper we present a MASH bandpass ΣΔ modulator for WCDMA applications. The signal bandwidth of the proposed modulator is 10 MHz, centered around an intermediate frequency (IF) of 70 MHz. Each ΣΔ modulator of the MASH structure is based on a two-path architecture, which allow us to obtain the desired in-band noise shaping zeros and reduce the power consumption. The ΣΔ modulator is implemented using a 0.18-nm CMOS technology and a sampling frequency of 180 MHz. The simulations at transistor level show a resolution of about 13 bits, with a bandwidth of 10 MHz, and a power consumption of about 90 mW, with a supply voltage of 1.8 V, resulting in a figure of merit (FoM<sub>BP</sub>) as low as about 0.15 pJ/conversion-level.
    Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on; 07/2010