The integration challenges of a low-k dielectric (k < 3) to form multi-level Cu interconnects for the next generation 0.1 μm CMOS technology are presented. Process improvements to overcome these challenges are highlighted which include etchfront control, resist poisoning, high aspect ratio metallization, and improved CMP planarity. The maturity of this technology has been demonstrated through high yield of a 4MB SRAM test vehicle.
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International; 02/2002