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ABSTRACT: Combining Mn oxide/Ta encapsulation and a self-aligned CuSiN barrier enhanced reliability of both wiring and dielectrics, reducing wiring resistance by 10%, compared with that of a control sample. The CuSiN barrier effectively concentrated Mn, resulting in a composite barrier consisting of Mn oxide, Mn silicate, and MnSiN forming on top of the Cu wiring. Mn concentration is attributed to the large difference in the standard heat of formation between Mn silicide and Cu silicide. The composite barrier that formed on top of the Cu wiring played a critical role in enhancing the reliabilities by suppressing surface Cu self-diffusion, vacancy diffusion, and Cu ion drift under electrical and thermal stresses. Suppressing the surface self-diffusion, for example, increased electromigration lifetime by a factor of 51. This combination technique has an advantage over a previous self-formation of a Mn oxide barrier in terms of reliabilities since the previous technique cannot form such a composite barrier on top of the Cu wiring.
IEEE Transactions on Electron Devices 11/2011; · 2.32 Impact Factor
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H. Kudo,
M. Haneda, T. Tabira,
M. Sunayama,
N. Ohtsuka,
N. Shimizu,
H. Ochimizu,
A. Tsukune,
T. Suzuki,
H. Kitada,
S. Amari,
H. Matsuyama,
T. Owada,
H. Watatani,
T. Futatsugi,
T. Nakamura,
T. Sugii
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ABSTRACT: To further enhance electro-migration resistance, we applied a self-aligned barrier technique to Cu wiring encapsulated with a MnO barrier. This combination of the self-aligned barrier and encapsulation techniques increased maximum current density to 9 times that of the conventional one. The Cu wiring fabricated by the combination of the two techniques also had greater resistance to stress-induced voiding set off by thermal stress. The combination of the two techniques also enhanced the lifetime of time-dependent dielectric breakdown by a factor of 160.
Interconnect Technology Conference, 2008. IITC 2008. International; 07/2008
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H. Kudo,
M. Haneda,
H. Ochimizu,
A. Tsukune,
S. Okano,
N. Ohtsuka,
M. Sunayama,
H. Sakai,
T. Suzuki,
H. Kitada,
S. Amari, T. Tabira,
H. Matsuyama,
N. Shimizu,
T. Futatsugi,
T. Sugii
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ABSTRACT: We successfully encapsulated Cu wiring with an ultra-thin self-forming barrier consisting of MnO and a bi-layer of MnO/Ta. TDDB test showed that the ILDs lifetime increased by a factor of 100 over that of our control sample. The encapsulated Cu wiring increased EM lifetime by a factor of more than 47. For via chains that are vulnerable to thermal stress, the encapsulated Cu wiring showed no SIV failure. The resistance of the encapsulated Cu wiring was 13% lower than that of the control sample. We expect encapsulated Cu wiring to have greater endurance to the electrical and thermal stresses for use in 32-nm nodes and beyond.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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H. Kitada,
T. Suzuki,
T. Kimura,
H. Kudo,
H. Ochimizu,
S. Okano,
A. Tsukune,
S. Suda,
S. Sakai,
N. Ohtsuka, T. Tabira,
T. Shirasu,
M. Sakamoto,
A. Matsuura,
Y. Asada,
T. Nakamura
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ABSTRACT: We tried to evaluate and predict the RC delay variability beyond the 45 nm copper interconnects technologies. The RC delay variability as a normalized delay time distribution, is caused by the line width/height variations due to the manufacturing process fluctuations. In order to evaluate the influence of the resistivity size effect precisely, we improved Fuchs-Sondheimer (F-S) and Mayadas-Shatzkes (M-S) models, in order to include the line height dependence of copper grain size, and applied it in the evaluation of the RC delay variability based on the SPICE simulation. In our results, we found that the RC delay variability in the 45nm node technology was relatively small, weakly dependent on the grid size and line height, and almost not affected by the size effect. On the contrary, in the 32 nm technology, the RC delay variability was about 2 times larger than the case ignoring the size effect and reached to the 20% of the average delay time at 3000 grid with 10% of line size fluctuation. In the 32 nm technology, the line height dependence of the RC delay variability was also strong and increased with decreasing line height. The influence of line height dependence of grain size reached about 1/5 or more of the total size effect in the RC delay variability.
International Interconnect Technology Conference, IEEE 2007; 07/2007
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H. Kudo,
H. Ochimizu,
A. Tsukune,
S. Okano,
K. Naitou,
M. Sakamoto,
S. Takesako,
T. Shirasu,
A. Asneil,
N. Idani, [......],
Y. Mizushima,
H. Matsuyama,
Y. Suzuki,
N. Shimizu,
K. Yanai,
M. Nakaishi,
T. Futatsugi,
I. Hanyu,
T. Nakamura,
T. Sugii
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ABSTRACT: According to the 45 nm BEOL technology node, we demonstrated that a homogeneous interlayer dielectric with dielectric constant of 2.25 has a substantial advantage in terms of RC delay reduction compared to other potential architectures such as hybrid and tri-level dielectrics. Combination of the homogeneous interlayer dielectric and ultra-thinned barrier metal lowered the RC delay to 86 % compared to that listed in the ITRS 2006 update.
International Interconnect Technology Conference, IEEE 2007; 07/2007
