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Publications (14)2.45 Total impact

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    ABSTRACT: Although the stacking of multiple strata to produce three-dimensional (3D) integrated circuits (ICs) improves interconnect length and hence reduces power and latency, it also results in the exacerbation of the thermal management challenge owing to the increased power density. There is a need for design tools to understand and optimise the trade-off between electrical and thermal design at the device and block levels. This study presents results from thermal-electrical co-optimisation for block-level floorplanning in a multi-die 3D IC under various manufacturing and physical design constraints. A method for temperature computation based on linearity of the governing energy equation is presented. This method is combined with previously reported electrical delay models for 3D ICs to simultaneously optimise both the maximum temperature and the interconnect length. It is shown that co-optimisation of thermal and electrical objectives results in a floorplan that is attractive from both perspectives. Physical design constraints because of cost-effective 3D manufacturing such as using fully or partly identical dies using reciprocal design symmetry (RDS), differentiated technology in each die and thinned die/wafer are discussed and their impact on the thermal-electrical co-optimisation is investigated. In some cases, the cheapest manufacturing choice, such as using identical die, for each layer may not result in optimal thermal and electrical design. Results presented in this work highlight the need for thermal and electrical co-design in multi-strata microelectronics, and for reconciling manufacturing and design considerations in order to develop practical design tools for 3D ICs.
    IET Computers & Digital Techniques 06/2011; · 0.28 Impact Factor
  • IET Computers & Digital Techniques. 01/2011; 5:169-178.
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    ABSTRACT: Three-dimensional (3D) interconnection technology offers several electrical advantages, including reduced signal delay, reduced interconnect power, and design flexibility. 3D integration relies on through-silicon vias (TSVs) and the bonding of multiple active layers to stack several die or wafers containing integrated circuits (ICs) and provide direct electrical interconnection between the stacked strata. While this approach provides several electrical benefits, it also offers significant challenges in thermal management. While some work has been done in the past in this field, a comprehensive treatment is still lacking. In the current work, analytical and finite-element models of heat transfer in stacked 3D ICs are developed. The models are used to investigate the limits of thermal feasibility of 3D electronics and to determine the improvements required in traditional packaging in order to accommodate 3D ICs. An analytical model for temperature distribution in a multidie stack with multiple heat sources is developed. The analytical model is used to extend the traditional concept of a single-valued junction-to-air thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. The impact of various geometric parameters and thermophysical properties on thermal performance of a 3D IC is investigated. It is shown that package and heat sink thermal resistances play a more important role in determining temperature rise compared to thermal resistances intrinsic to the multidie stack. The improvement required in package and heat sink thermal resistances for a 3D logic-on-memory implementation to be thermally feasible is quantified. An increase in maximum temperature in a 3D IC compared to an equivalent system-in-package (SiP) is predicted. This increase is found to be mainly due to the reduced chip footprint. The increased memory die temperature in case of memory-on-logic integration compared to a SiP implementation is identified to be a sig- - nificant thermal management challenge in the future. The results presented in this paper may be useful in the development of thermal design guidelines for 3D ICs, which are expected to help maximize the electrical benefits of 3D technology without exacerbating thermal management issues when implemented in early-stage electrical design and layout tools.
    IEEE Transactions on Components and Packaging Technologies 04/2010; · 0.94 Impact Factor
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    ABSTRACT: Emerging 3-D multistrata system integration offers the capability for high density interstratum interconnects that have short lengths and low parasitics. However, 3-D integration is only one way to accomplish system integration and it must compete against established system integration options such as system-on-a-chip (SoC) and system-in-a-package. We discuss multiple tradeoffs that need to be carefully considered for choosing 3-D integration over other integration schemes. The first step toward enabling 3-D design is characterizing the new interstratum connection elements, microconnects and through-Si vias, in a bonded 3-D technology. We have used both analytical- and simulation-based approaches to analyze the parasitic characteristics of interstratum connections between bonded 3-D stratum, and have compared the interstratum power and performance with SoC global interconnects, taking into account the impact of technology scaling. The specific elements in an interstratum connection and their electrical properties strongly depend on the choice of 3-D integration architecture, such as face-to-face, back-to-face, or the presence of redistribution layer for bonding. We present an adaptive interstratum IO circuit technique to drive various types of interstratum connections and thus enable 3-D die reuse across multiple 3-D chips. The 3-D die/intellectual property reuse concept with the adaptive interstratum IO design can be applied to design 3-D ready dice to amortize additional 3-D costs associated with strata design, test, and bonding process.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 03/2010; 18:450-460. · 1.22 Impact Factor
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    ABSTRACT: The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance. In this paper, we present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane. We also analyze the impact of technology scaling on TSV electrical parasitics, and investigate the power and delay trend in 3-D interstratum IO drivers with those of global wire in 2-D circuits over various technology nodes. We estimate the global wire length necessary to produce an equivalent 3-D IO delay, a metric useful in early stage design tools for 3D floorplanning that considers the electrical characteristics of 3D connections with TSVs and microconnects.
    Microelectronics Journal. 01/2010;
  • Scott K. Pozder, Robert E. Jones
    06/2009: pages 333-352;
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    ABSTRACT: The bonding of multiple silicon strata to form stacked circuits with high bandwidth connections, increased circuit densities, decreased latency and the capability to stack disparate technologies is increasingly gaining interest in the microelectronics industry. Stacking has been demonstrated using bom dielectric‐to‐dielectric and metal‐to‐metal bonds for die and wafer stratum bonding. The considerable thermal, mechanical and electromigration reliability challenges resulting from such bonding has been the focus of some recently reported work. In mis paper, the bond reliability of various bonding types, including wafer‐to‐wafer dielectric bond, die‐to‐wafer Cu∕Sn‐to‐Cu bond and a simultaneous organic adhesive with Cu∕Sn‐to‐Cu bond is discussed. Thermomechanical and electromigration characterization of the die‐to‐wafer 3D structures is also discussed. Results indicate that the intrinsic reliability of these structures can be as robust as current 2D technologies.
    AIP Conference Proceedings. 06/2009; 1143(1):213-223.
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    ABSTRACT: While the stacking of multiple strata to produce 3D integrated circuits improves interconnect length and hence reduces power and latency, it also results in the exacerbation of the thermal management challenge due to the increased power density. There is a need for design tools to understand and optimize the trade-off between electrical and thermal design at the device and block level. This paper presents results from thermal-electrical co-optimization for block-level floorplanning in a multi-die 3D integrated circuit. A method for temperature computation based on linearity of the governing energy equation is presented. This method is shown to be faster and more accurate than previously used resistance-network based approaches and full-scale FEM simulations. This method is combined with previously reported electrical delay models for 3D ICs to simultaneously optimize both the maximum temperature and the interconnect length. Results outline the various trade-offs between thermal and electrical considerations. It is shown that co-optimization of thermal and electrical objectives results in a floorplan that is attractive from both perspectives. Constraints placed by the 3D IC manufacturing process on design are outlined, showing that the cheapest manufacturing options may not result in optimal electrical and thermal design. In particular, the wafer-on-wafer bonding process requires the two die to be identical, which results in a severe design constraint, particularly on the thermal goal due to the overlap of high power density blocks. Results presented in this work highlight the need for thermal and electrical co-design in multistrata microelectronics, and for reconciling manufacturing and design considerations in order to develop practical design tools for 3D integrated circuits.
    ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability; 01/2009
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    ABSTRACT: Each stratum in a 3D chip usually requires a unique mask set which increases the mask cost for a multi-strata chip compared to its 2D counterpart. We present a novel design technique using reciprocal design symmetry (RDS) that allows a mask set (or at least a majority of these) to be used for different strata while still achieving vertical placement and connection of different design functionalities. We demonstrate an application of RDS using a detailed example of a 3D dual-core microprocessor with analyses of various design complexity and testability issues, and a comprehensive simulation and comparison of its thermal characteristics. The coarse grained partitioning of self-contained functional units achieved with RDS is suitable for early adoption of 3D technology as well as for long-term application to low cost system integration due to less redesign effort, design tool requirements, and better testability of each stratum before and after bonding.
    10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA; 01/2009
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    ABSTRACT: The simultaneous formation of Cu/Sn microconnects and an adhesive bond during wafer level thermal compression bonding was evaluated using a 3D enabled single metal level test die and wafer. The wafer level bond process relied on locally dispensed adhesive to fix the dice to the wafer prior to bonding and to become a permanent bond during the bonding process. The die-to-wafer microconnect resistance was measured for micropad pitches of 59, 64, and 69 ¿m. The robustness of the Cu/Sn and adhesive bond was demonstrated by thinning the bonded die to 50 ¿m. Package level reliability testing of parts that were wire bonded into a thermally enhanced plastic ball grid array (PBGA) package indicates good reliability behavior and the absence of any intrinsic reliability-related issues in the microconnects.
    Interconnect Technology Conference, 2008. IITC 2008. International; 07/2008
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    ABSTRACT: 3D interconnect technology has attracted significant interest in the recent past as a means for enabling faster and more efficient integrated circuits (ICs). 3D integration relies on through-silicon vias (TSVs) and bonding of multiple active layers. While this approach provides several electrical benefits, it also offers significant challenges in thermal management. While some work has been done in the past in this field, a comprehensive treatment is still lacking. In the current work, analytical and finite-element models of heat transfer in 3D electronic circuits are developed. The models are used to investigate the limits of thermal feasibility of 3D electronics and to determine the improvements required in traditional packaging in order to accommodate 3D ICs. An analytical model for temperature distribution in a multi-die stack with multiple heat sources is developed. The analytical model is used to extend the traditional concept of thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. The impact of various geometric parameters and thermophysical properties on thermal performance of a 3D IC is investigated. It is shown that package thermal resistances play a more important role in determining temperature rise compared to thermal resistances intrinsic to the 3D technology, including thermal resistance of bonding layers and TSVs. As a result, an improved bonding layer or TSV thermal resistance does not offer much thermal benefit. An increase in thermal resistance of a 3D IC is predicted as compared to an equivalent System-on-Chip (SoC). This increase is found to be mainly due to the reduced chip footprint. The amount of improvement required in package and heat sink thermal resistances for a logic-on-memory 3D implementation to be thermally feasible is quantified. The results presented in this paper are expected to aid in the development of thermal design guidelines for 3D ICs.
    Thermal and Thermomechanical Phenomena in Electronic Systems, 2008. ITHERM 2008. 11th Intersociety Conference on; 06/2008
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    ABSTRACT: There is significant interest in 3D interconnect technology due to its capability to provide fast, efficient inter-die interconnects at a minimum package footprint. Intermetallic Cu-Sn bonding has been widely investigated for 3D interconnects. However, the electromigration (EM) intrinsic reliability of the 3D Cu-Sn die-to-die microconnects has not been reported. In this paper the EM performance of 3D Cu-Sn microconnects formed by thermo-compression bonding is investigated and the failure mechanisms are discussed. The 3D stacked dice were assembled in wire bond ceramic packages and EM tests were conducted in both air and nitrogen ambient at various temperatures. Microconnect chain and Kelvin structure's failure lifetime and the mean time to failure (MTTF) were measured. The failure analysis has been conducted and the possible failure mechanism has been proposed.
    Electronic Components and Technology Conference, 2008. ECTC 2008. 58th; 06/2008
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    ABSTRACT: Three dimensional stacked circuits having multiple active semiconductor levels rely on the development of strata bonding, micro connects between strata, through strata vias (TSV) and a wafer thinning process. Progress in the each of these process technologies for 3D strata stacking is opening the path to more robust and capable 3D process integrations.
    International Interconnect Technology Conference, IEEE 2007; 07/2007
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    ABSTRACT: A three-dimensional (3D) wafer-to-wafer integration technology has been developed using face-to-face dielectric wafer bonding, followed by wafer thinning and backside interconnect formation. The key technologies required for this integration include: reliable defect free direct dielectric wafer bonding, precise wafer-to-wafer alignment, backside thinning, deep inter-strata via (ISV) formation, and wafer patterning alignment across strata. Electrical measurements indicate continuity of ISV chains for all but the smallest vias.
    International Interconnect Technology Conference, IEEE 2007; 07/2007