Dong Hun Shin

University of California, Santa Barbara, Santa Barbara, CA, United States

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Publications (5)2.94 Total impact

  • Piljae Park, Dong Hun Shin, C.P. Yue
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    ABSTRACT: This paper presents circuit techniques to achieve high linearity and good isolation for CMOS transmit/receive (T/R) switches above 20 GHz. A comparison between the conventional symmetrical and the proposed asymmetrical switch topology is presented with an emphasis on the linearity performance. The substrate loading effects on T/R switch figure of merit are analyzed quantitatively based on a compact model of triple-well (TW) NMOS device. AC-floating bias techniques used for the T/R switch and the associated performance tradeoffs are discussed. By combining these techniques, an LC-tuned 24-GHz single-pole double-throw T/R switch is implemented in a 90-nm TW CMOS process. The switch uses 1.2-V digital control signals for both T/R mode selection and source/drain biases. The design achieves a measured P<sub>1dB</sub> of 28.7 dBm, which represents the highest linearity reported to date for CMOS millimeter-wave switches. The measured insertion loss and return loss at 24 GHz are better than 3.5 and 10 dB, respectively.
    IEEE Transactions on Microwave Theory and Techniques 05/2009; · 2.94 Impact Factor
  • C. Patrick Yue, Dong Hun Shin
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    ABSTRACT: This paper presents a cell-based modeling and design platform for high-frequency analog ICs to shorten design cycle time and to minimize the risk for mask re-spin. Based on a pre-characterized analog sub-circuit cell library, which contains not only active devices and passive components but also routing interconnects. This methodology systematically alleviates modeling inaccuracy at high frequencies due to the difference in the layout between device test structures and actual circuit implementation. By exploiting the modularity in analog circuits at the sub-circuit level, the proposed design platform achieves a balance between design flexibility and modeling accuracy compared. The macro modeling techniques the sub-circuit cells will be described along with measurement results from a characterization test chip. The design and measured results of an UWB LNA utilizing the cell library will be presented.
    Radio-Frequency Integration Technology, 2007. RFIT 007. IEEE International Workshop on; 01/2008
  • Source
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    ABSTRACT: This paper presents an LC-tuned, 24-GHz single-pole double-throw (SPDT) transmit/receive (T/R) switch implemented in 90-nm CMOS. The design focuses on the techniques to increase the power handling capability in the transmit (Tx) mode under 1.2-V operation. The switch achieves a measured P<sub>-1dB</sub> of 28.7 dBm, which represents the highest linearity, reported to date, for CMOS millimeter-wave T/R switches. The transmit and receive (Rx) branches employ different switch topologies to minimize the power leakage into the Rx path during Tx mode, and hence improve the linearity. To accommodate large signal swing, AC floating bias is applied using large bias resistors to all terminals of the switch devices. Triple-well devices are utilized to effectively float the substrate terminals. The switch uses a single 1.2-V digital control signal for T/R mode selection and for source/drain bias. The measured insertion loss is 3.5 dB and return loss is better than -10 dB at 24 GHz.
    Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE; 01/2008
  • Source
    Dong Hun Shin, Jaejin Park, C.P. Yue
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    ABSTRACT: This paper presents the design of a 3-5-GHz CMOS ultra-wideband (UWB) Iow-noise amplifier (LNA) utilizing an on-chip transformer to achieve low-power operation and to realize a compact input matching network. Detailed analyses of the input match, voltage gain, and noise figure of the LNA are provided. Implemented in 0.13-mum CMOS, the LNA achieves a maximum power gain of 16.2 dB, an input return loss of greater than 11.0 dB, and a minimum noise figure of 2.8 dB for the 3-5-GHz UWB while consuming only 6.7 mW from a 1.2-V supply. The active area of the fabricated CMOS UWB LNA is 0.32 mm<sup>2</sup>.
    Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian; 12/2007
  • Dong Hun Shin, C.P. Yue
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    ABSTRACT: This paper presents, for the first time, a cell-based modeling and design platform for RFICs aiming to shorten design cycle time by eliminating iterations between schematic and post-layout simulations and to minimize the risk for costly mask re-spin. Based on a pre-characterized RF sub-circuit cell library, which contains not only active devices and passive components but also routing interconnects, this methodology systematically alleviates the common RF model inaccuracy due to layout discrepancies between actual circuits and device model test structures. By exploiting the modularity in RF circuits at the sub-circuit level, the proposed design platform achieves a balance between circuit design flexibility and device model accuracy compared to the conventional approach of using pre-characterizing single transistors. This paper describes the implementation of the parameterized sub-circuit cell layout and the macro modeling techniques for a 0.13-mum CMOS RF sub-circuit cell library. Measurement results from a characterization test chip for validating the macro circuit models are presented
    Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 IEEE; 07/2006

Publication Stats

46 Citations
2.94 Total Impact Points

Institutions

  • 2007–2009
    • University of California, Santa Barbara
      • Department of Electrical and Computer Engineering
      Santa Barbara, CA, United States
  • 2006
    • Carnegie Mellon University
      • Department of Electrical and Computer Engineering
      Pittsburgh, Pennsylvania, United States