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ABSTRACT: Efficiency degradation effects of power combining transformers with partially disabled inputs are quantitatively analyzed. To improve efficiencies in lower-power modes of a multi-mode class-AB power amplifier (PA), a discrete resizing technique is introduced in combination with a parallel-combining transformer (PCT). The two-stage PA implemented in a 0.18-μm CMOS technology also includes varactor-based tunable matching circuits. The design method involves parallel-combining of two power stages, each of which are divided into three sub-cells to facilitate discrete resizing. The parallel-combining of concurrently resized power cells minimizes undesired power loss through the transformer and helps the PA to utilize the transformer efficiency maximally independent of the number of combining cells. When operating in the high-power mode, the PA exhibits a peak output power of 31 dBm with a PAE of 34.8%. Power back-offs are realized by discretely turning off parallel sub-amplifier cells concurrently, achieving output power levels of 26 dBm and 22.3 dBm with respective PAE of 22.5% and 15%. The EVM has been measured with IEEE 802.11g WLAN and 802.16e WiMAX modulated signals in three operation modes. In the high-power mode, the PA dissipates 590 mA from a 3.3 V supply.
IEEE Journal of Solid-State Circuits 06/2011; · 3.23 Impact Factor
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ABSTRACT: A cascode configuration in class-E CMOS power amplifiers (PAs) provides high reliability with respect to breakdown considerations. However, it causes a power loss due to the slow transition of a common-gate device from the triode region to the cut-off region. To minimize the power loss of cascode class-E CMOS PAs, we propose a charging acceleration technique, CAT. This method incorporates a capacitive element between the drain and the source of a common-gate device in a cascode configuration, accelerating the charging speed responsible for turning off a common-gate device instantly after a common-source device is turned off and thus minimizing power loss from the device. We compared the performance of the proposed cascode class-E PA to that of the conventional cascode class-E PA using a 0.18- CMOS process. With a 3.3-V power supply, the proposed fully-integrated CMOS PA achieves 30.7 dBm of maximum output power and 45.6% of power-added efficiency (PAE) with a dynamic range of 40 dB at 1.6 GHz. According to measurements, the proposed cascode class-E PA shows improvement in PAE over the conventional class-E PA of between 5% and 9% in a 1.5 to 2.0 GHz range.
IEEE Journal of Solid-State Circuits 11/2010; · 3.23 Impact Factor
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ABSTRACT: A dual-mode tunable CMOS power amplifier in a standard 0.18-μm CMOS process is presented. The tunable PA is designed for the IEEE 802.11g application with enhanced low-power efficiency. A reconfigurable matching network along with resizing of a PA core device is exploited corresponding to the operation modes: high-power and low-power modes. The tunable PA demonstrates measured output powers of 15.7 dBm with the PAE of 18.5% for high-power mode and 10 dBm with the PAE of 15.1% for low-power mode while satisfying EVM and spectrum mask requirements of the 802.11g specification. More than 130% efficiency-enhancement is achieved by incorporating the proposed low-power mode up to 10-dBm output power, which is a significant enhancement. To our knowledge, this is the first fully-integrated tunable PA with on-chip tunable matching network using a standard CMOS process.
Microwave Conference (EuMC), 2010 European; 10/2010
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ABSTRACT: A fully integrated power amplifier operating at switching and linear mode is implemented using 0.18-μm CMOS technology. To maximize performance for both operation modes, the fundamental load impedances are optimized with a variable capacitor for GSM and EDGE application. For GSM application, 32 dBm of the output power with 45 % of the drain efficiency is achieved at 1.76 GHz. With EDGE modulation signal at 1.76 GHz, error vector magnitude (EVM) has an RMS value of less than 5 % up to 27.5 dBm of the output power, and 28.1 % of modulated PAE is achieved at this power. The output spectrum is confined within the inside of mask up to 27.5 dBm of the output power.
Microwave Symposium Digest (MTT), 2010 IEEE MTT-S International; 06/2010
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ABSTRACT: A highly efficient CMOS linear power amplifier for WCDMA applications with feedback bias technique is presented. The method involves connecting the gates of common-gate devices of the driver stage and the power stage in cascode configurations by a feedback network for enhancing linearity. To achieve high efficiency and linearity simultaneously, large-signal IMD minimum (IMD sweet spot) is properly used at the desired output power level. The proposed PA was fabricated in a 0.18-μm CMOS technology. The experimental results demonstrate a gain of 26 dB, a maximum output power of 26 dBm with 46.4% of peak PAE, and a linear output power of 23.5 dBm with 40% PAE using a 3GPP WCDMA modulated signal. Both simulation and measurement results show an excellent large-signal IMD minimum at the output power using a WCDMA modulated signal.
Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE; 06/2010
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ABSTRACT: We propose a new method of power combining for a parallel-combining-transformer (PCT)-based CMOS linear power amplifier (PA). The power cell in parallel paths is divided into three sub-cells to implement device resizing for discrete power control. Concurrent power combining of sub-power-cells utilizes the maximum available transformer efficiency even at the low-power mode, boosting overall PA efficiency. When all sub-power-cells are enabled, the PA exploits output power of 30.7 dBm with PAE of 35.8%. Power back-offs of 6 dB and 12 dB are achieved by discretely turning off sub-cells, showing output power of 25 dBm and 19 dBm with PAE of 19.8% and 10.5%, respectively. With 802.11g WLAN modulated signal used for linearity test, the PA shows 21-dBm output power satisfying -25-dB EVM requirements consuming 560 mA from 3.3 V power supply.
Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE; 06/2010
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J. Solid-State Circuits. 01/2010; 45:2184-2197.
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IEEE Trans. on Circuits and Systems. 01/2010; 57-I:725-734.
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ABSTRACT: A fully integrated 2.4 GHz CMOS power amplifier (PA) in a standard 0.18 mum CMOS process is presented. Using a parallel-combining transformer (PCT) and gate bias adaptation, a discrete power control of the PA is achieved for enhancing the efficiency at power back-off. With a 3.3 V power supply, the PA has a peak drain efficiency of 33% at 31 dBm peak output power. By applying discrete power control, a reduction of 650 mA in current consumption can be achieved over the low output power range while satisfying the EVM requirements of WLAN 802.11g and WiMAX 802.16e signals.
IEEE Microwave and Wireless Components Letters 08/2009; · 1.72 Impact Factor
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ABSTRACT: The highly efficient CMOS power amplifier module (PAM) is designed for quad-band cellular handsets comprising GSM850, EGSM, DCS, PCS and supports Class 12 general packet radio service (GPRS) multi-slot operation. This module integrates an input matching network, a complete power control, and a thermal, over current, and load mismatch protection in a standard RF CMOS process and also contains a high-Q integrated passive device (IPD) for an output-matching network. The modular integration of the IPD makes it easier to manufacture PA module and also guarantees higher power-added efficiency (PAE) when compared with PAM products based on other technologies.
Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE; 07/2009
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ABSTRACT: A high PA and an antenna switch were implemented in a single die with low noise amplifier to study feasibility of integration of all the RF front end components in a standard bulk CMOS process. Low voltage operation which is the biggest obstacle to implement a high power amplifier and a high power switch in the CMOS technology were resolved to by employing power combining technique using transformer and adaptive voltage swing distribution techniques. 30 dBm output power was obtained at 2 GHz with -40 dBc second and third harmonics. This is very promising data to open the possibility to integrate high power components in a standard CMOS process at cellular applications.
Microwave Conference, 2008. APMC 2008. Asia-Pacific; 01/2009
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Kyu Hwan An,
Ockgoo Lee,
Hyungwook Kim,
Dong Ho Lee,
Jeonghu Han,
Ki Seok Yang,
Younsuk Kim,
Jae Joon Chang,
Wangmyong Woo,
Chang-Ho Lee,
Haksun Kim,
J. Laskar
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ABSTRACT: Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented. For the high power CMOS PA design, two types of transformers, series-combining and parallel-combining, are fully analyzed and compared in detail to show the parasitic resistance and the turn ratio as the limiting factor of power combining. Based on the analysis, two kinds of parallel-combining transformers, a two-primary with a 1:2 turn ratio and a three-primary with a 1:2 turn ratio, are incorporated into the design of fully-integrated CMOS PAs in a standard 0.18-mum CMOS process. The PA with a two-primary transformer delivers 31.2 dBm of output power with 41% of power-added efficiency (PAE), and the PA with a three-primary transformer achieves 32 dBm of output power with 30% of PAE at 1.8 GHz with a 3.3-V power supply.
IEEE Journal of Solid-State Circuits 06/2008; · 3.23 Impact Factor
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ABSTRACT: In this paper, a novel monolithic voltage-boosting parallel-primary transformer is presented for the fully integrated CMOS power amplifier design. Multiple primary loops are interweaved in parallel to combine the AC currents from multiple power devices while the higher turn ratio of a secondary loop boosts AC voltages of the combined primary loops at the load of the secondary loop. The proposed interweaved structure is much more compact and separable from power devices, avoiding potential instability. To verify the feasibility of this power combining method, the fully integrated CMOS switching power amplifier was implemented in a standard 0.18-mum technology. The power amplifier successfully demonstrated a measured output power of 1.3 W and a measured power added efficiency (PAE) of 41% to a 50-Omega load with a 3.3-V power supply at 1.8 GHz operation.
Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE; 07/2007
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ABSTRACT: This paper newly presents a push-pull parallel-combined CMOS power amplifier (PA) and its analysis of operation. The proposed class-E CMOS PA incorporates the push-pull parallel-combined power devices with the 1:1:2 (two single-turn primary windings and a two-turn secondary winding) step-up on-chip transformer. The PA is fully integrated in a standard 0.18-mum CMOS technology without any external balun or matching networks. The operation of the PA with a multi-turn on-chip transformer is substantially analyzed in order to optimize the device size and its structure. Experimental data demonstrates the output power of 2-watt and the power-added efficiency (PAE) of more than 30% with a 3.3-V of power supply at 1.8 GHz. This is the new demonstration of the compact fully integrated CMOS PA with 2-watt of output power with very stable operation at 1.8 GHz range.
Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE; 07/2007
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ABSTRACT: This paper presents a new polar transmitter architecture that employs analog predistortion to provide substantially instantaneous correction of amplitude and phase errors in RF PAs. This approach enables to enhance the linear output power capability and efficiency of a PA, simultaneously. Unlike conventional architectures using a closed-loop feedback, no downconversion receiver is included in the transmitter. Moreover, only even-order distortion components are used to predistort the input signal in a multiplicative manner so that the effective correction bandwidth is greatly enhanced. For validation of the architecture, a PA circuit model was designed, based upon the TSMC 0.18-um CMOS technology. In the simulation results, the proposed architecture reduced PA nonlinearity from 2 dB to 0.5 dB for gain and from 18deg to plusmn0.5deg for phase. Also, the simulation results exhibited EVMs of less than 0.5% in RMS and 5% in peak, a PAE of 58% at the output power of 33 dBm.
Microwave Conference, 2006. APMC 2006. Asia-Pacific; 01/2007
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Kyu Hwan An
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ABSTRACT: The explosive growth of the wireless market has increased the demand for low-cost, highly-integrated CMOS wireless transceivers. However, the implementation of CMOS RF power amplifiers remains a formidable challenge. The objective of this research is to demonstrate the feasibility of CMOS RF power amplifiers by compensating for the RF performance disadvantages of CMOS technology. This dissertation proposes a parallel-combining transformer (PCT) as an impedance-matching and output-combining network. The results of a comprehensive analysis show that the PCT is a suitable solution for watt-level output power generation in cellular applications. To achieve high output power and high efficiency, the work presented here entailed the design of a class-E switching power amplifier in a 0.18-μm CMOS technology for GSM applications and, with the suggested power amplifier design technique, successfully demonstrated a fully-integrated RF front-end consisting of a power amplifier and an antenna switch. This dissertation also proposed an efficiency enhancement technique at power back-off. In an effort to save current in the power back-off while satisfying the EVM requirements, a class-AB linear power amplifier was implemented in a 0.18-μm CMOS technology for WLAN and WiMAX applications using a PCT as well as an operation class shift between class-A and class-B. Thus, the research in this dissertation provides low-cost CMOS RF power amplifier solutions for commercial products used in mobile wireless communications.
