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ABSTRACT: <sub>DS(on)</sub> *A = 36.2 mQmm<sup>2</sup> at a breakdown voltage of 60 V. The integration of the devices in the CMOS base process uses five additional photo masks.
Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European; 10/2007
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T. Uhlig,
A. Bemmann,
C. Ellmers, F. Furnhammer,
M. Gross,
Y.H. Hu,
J. Liu,
R.-R. Ludwig,
M. Reinhold,
M. Stoisiek,
E. Votintseva,
M. Wittmaack
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ABSTRACT: A new smart power SOC IC process including up to 50V HV-MOS transistors, SONOS principle based non-volatile memory components and analog devices using an advanced 0.18μm platform is presented. Process architecture and device portfolio are focused on automotive applications e.g. sensor signal conditioning and integrated output drivers. HV-MOS and SONOS integration as well as device properties are discussed with regard to reliability aspects. Additionally key features of NPN bipolar transistors and depletion NMOST are given.
Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on; 06/2007
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ABSTRACT: A model is for presented a three-terminal MOS varactor for RF applications. The accuracy of the MOS varactor model is demonstrated by comparing simulation and measured device data at room and high temperatures. The relative mean error of the S-parameters between the measured and simulated data are less than 4%.
Electronics Letters 12/2002; · 0.96 Impact Factor
