Publications (2)0 Total impact
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ABSTRACT: Based on the noise parameter expressions of the proposed CMOS LNA topology, the design principles, advantages, and limitations of the power-constrained simultaneous noise and input matching technique are discussed. As a demonstration for the proposed design principle, a 433 MHz low-power CMOS LNA is implemented in SMIC's 0.18 mum CMOS technology. Measured results show a good agreement with the proposed design principle and theoretical analysis.
Conference Paper: Low-power 915MHz CMOS LNA design optimization techniques for RFID[Show abstract] [Hide abstract]
ABSTRACT: According to the definition of noise figure, this paper presents a detailed analysis of the noise parameter of a low noise amplified (LNA) in a CMOS cascode topology with the source degeneration inductance and gate shunt capacitance. Based on the derived equations, the important application of this topology is discussed and a low power UHF CMOS LNA is optimized for RFID. The simulated results show a noise figure of 0.7dB, a power gain of 12.5dB, and an IIP3 of -4dBm while dissipating 2.1mA from a 1.8V supply. As a result, very low noise figures become possible already at very low power consumption levels.Microwave and Millimeter Wave Technology, 2007. ICMMT '07. International Conference on; 05/2007