[Show abstract][Hide abstract] ABSTRACT: An array of simple programmable processors is implemented in 0.18 mum CMOS and contains 36 asynchronously clocked independent processors. Each processor occupies 0.66 and is fully functional at a clock rate of 520-540 MHz at 1.8 V and over 600 MHz at 2.0 V. Processors dissipate an average of 32 mW under typical conditions at 1.8 V and 475 MHz, and 2.4 mW at 0.9 V and 116 MHz while executing applications such as a JPEG encoder core and a fully compliant IEEE 802.11 a/g wireless LAN baseband transmitter.
IEEE Journal of Solid-State Circuits 04/2008; · 3.06 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Abstractó This paper presents the architecture of an Asyn- chronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and energy efciency . The AsAP processor calculates DSP applications with high energy-efciency , is capable of high-performance, is easily scalable, and is well-suited to future fabrication technologies. It is composed of a 2-D array of simple single-issue programmable processors interconnected by a recongurable mesh network. Processors are designed to capture the kernels of many DSP algorithms with very little additional overhead. Each processor contains its own tunable and haltable clock oscillator, and pro- cessors operate completely asynchronously with respect to each other in a globally asynchronous locally synchronous (GALS) fashion. A 6 6 AsAP array has been designed and fabricated in a 0.18 CMOS technology. Each processor occupies 0.66
Journal of Signal Processing Systems 01/2008; 53:243-259. · 0.55 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Many emerging and future applications require significant levels of complex digital signal processing and operate within limited power budgets. Moreover, dramatically rising VLSI fabrication and design costs make programmable and reconfigurable solutions increasingly attractive. the ASAP project addresses these challenges with a chip multiprocessor composed of simple processors with small memories, achieving high energy efficiency and throughput in a small chip area.
[Show abstract][Hide abstract] ABSTRACT: An array of simple programmable processors designed for DSP applications is implemented in 0.18mum CMOS and contains 36 asynchronously clocked independent processors. The processors operate at 475MHz, and each processor has a maximum power of 144mW at 1.8V and occupies 0.66 mm<sup>2</sup>