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ABSTRACT: This paper presents an all digital delay-locked loop (DLL) which achieves low jitter and stable duty cycle correction (DCC) operation. Since the DLL has dual DCC circuit, with the combinations of two DCC circuits, the DLL can correct +12.9% and -6.13% duty error under 2% at 333 MHz with 1.6 V. The DLL operates up to 1.67 GHz with 1.8 V and 1.78 GHz with 2.0 V supply voltage, and its peak-to-peak jitter at 1.4 GHz with 1.8 V is 29 ps. The power dissipations are 4.2 mW (5 mW) at 100 MHz and 19.8 mW (29.5 mW) at 1 GHz with 1.5 V (1.8 V) supply voltage with the help of the update gear circuit from the previous work. And the DLL is fabricated with 54-nm DRAM CMOS technology. The active area of the DLL is 0.11 mm<sup>2</sup>.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10/2011; · 1.22 Impact Factor
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IEEE Trans. VLSI Syst. 01/2011; 19:1718-1722.
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Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings; 01/2010
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ABSTRACT: This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 mum CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7 ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm<sup>2</sup>.
IEEE Journal of Solid-State Circuits 10/2009; · 3.23 Impact Factor
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International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan; 01/2009
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IEEE Trans. VLSI Syst. 01/2009; 17:1461-1469.
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ABSTRACT: A wide-range low-jitter digital DLL using 0.18 um single-poly four-metal CMOS technology is proposed that uses an open-loop time-to-digital converter (TDC)-based DCC circuit with 10 cycles of maximum locking time by virtue of pulse width detection scheme. In addition, the DLL uses a semi dual delay line to remove the boundary switching problem and to optimize its area and power consumption. Thus, the proposed DLL operates over a frequency range from 170 MHz to 1.4 GHz. The peak-to-peak jitter is 13.8 ps at 1.4 GHz and the power consumption is reduced to 27 mW.
Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European; 10/2008
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Won-Joo Yun,
Hyun Woo Lee, Dongsuk Shin,
Shin Deok Kang,
Ji Yeon Yang,
Hyeng Ouk Lee,
Dong Uk Lee,
Sujeong Sim,
Young Ju Kim,
Won Jun Choi, [......],
Hyang Hwa Choi,
Hyung Wook Moon,
Seung Wook Kwack,
Jung Woo Lee,
Young Kyoung Choi,
Nak Kyu Park,
Kwan Weon Kim,
Young Jung Choi,
Jin-Hong Ahn,
Ye Seok Yang
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ABSTRACT: We design a DLL that has a slew-rate controlled duty-cycle-correction (DCC) with a fully digital controlled duty-cycle-error detector and has the update gear circuit to shift update mode for low power consumption. The DLL is composed of a dual loop and two types of digital DCC, at the input and output, which have a higher DCC capability when combined. We also design a clock receiver that generates a robust clock from a poor clock source.
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International; 03/2008
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ABSTRACT: A portable multiphase clock generator, independent of input duty ratio, has been developed. The proposed open-loop and full-digital architecture has a fast lock time of two clock cycles and is a simple, robust and portable IP. In addition, the complementary delay line is implemented to achieve high phase resolution at a wide frequency range. The generator has been implemented in a 0.18 um CMOS process and operates at variable input frequencies ranging from 800 MHz to 1.6 GHz.
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
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ABSTRACT: An ADDLL is designed to achieve low jitter, fast lock time and nearly 50% duty cycle with an open-loop duty-cycle corrector. The ADDLL operates over a frequency range from 440MHz to 1.5GHz with 15 cycles of maximum lock-in time and occupies 0.053mm<sup>2</sup> in 0.18mum 1.8V CMOS. The peak-to-peak jitter is 7ps at 1.5GHz and the power consumption is 43mW.
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International; 03/2007
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IEICE Transactions. 01/2006; 89-A:1552-1557.
