B. Froment

Publications (3)2.85 Total impact

• Source

  Available from: P.P. Absil

  Article: Schottky-Barrier Height Lowering by an Increase of the Substrate Doping in PtSi Schottky Barrier Source/Drain FETs

  G. P. Lousberg, H. Y. Yu, B. Froment, E. Augendre, A. De Keersgieter, A. Lauwers, M.-F. Li, P. Absil, M. Jurczak, S. Biesemans
  [show abstract] [hide abstract]
  ABSTRACT: In this letter, the Schottky-barrier height (SBH) lowering in Pt silicide/n-Si junctions and its implications to Schottky-barrier source/drain p-field-effect transistors (p-SBFETs) are studied experimentally and numerically. We demonstrate that the increase of the n-Si substrate doping is responsible for a larger hole SBH lowering through an image-force mechanism, which leads to a substantial gain of the drive current in the long-channel bulk p-SBFETs. Numerical simulations show that the channel doping concentration is also critical for short-channel p/n-silicon-on-insulator SBFET performance
  IEEE Electron Device Letters 03/2007; · 2.85 Impact Factor
• Source

  Available from: P.P. Absil

  Conference Proceeding: Experimental and simulation study of the Schottky barrier lowering by substrate doping variation for PtSi Source/Drain SBFETs

  G.P. Lousberg, H.Y. Yu, B. Froment, M.F. Li, E. Augendre, A. De Keersgieter, C. Demeurisse, S. Brus, B. Degroote, T. Hoffmann, A. Lauwers, M. DePotter, S. Kubicek, K. Anil, P. Absil, M. Jurczak, S. Biesemans
  [show abstract] [hide abstract]
  ABSTRACT: In this paper, the authors study experimentally and numerically the Schottky barrier height (SBH) lowering of Pt silicide/n-Si diodes and its implications to Schottky-barrier (SB) source/drain p-FETs. The authors demonstrate that hole SBH can be lowered through an image-force mechanism by increasing the n-Si substrate doping, which leads to a substantial gain of the drive current in the long-channel bulk p-SBFETs. Numerical simulations show that the channel doping concentration is also critical for short-channel n- & p-SOI SBFETs performance
  Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European; 10/2006
• Conference Proceeding: Demonstration of a New Approach Towards 0.25V Low-Vt CMOS Using Ni-Based FUSI

  H.Y. Yu, J.A. Kittl, A. Lauwers, R. Singanamalla, C. Demeurisse, S. Kubicek, E. Augendre, A. Veloso, S. Brus, C. Vrancken, [......], M. Demand, A. Rothchild, B. Froment, M. van Dal, K.De. Meyer, M.F. Li, J.D. Chen, M. Jurczak, P.P. Absil, S. Biesemans
  [show abstract] [hide abstract]
  ABSTRACT: This report discusses a new and practical approach to implement low V_t bulk CMOS using Ni-based FUSI MOSFETs. On the nFET, we demonstrate for the first time that incorporating Yb by ion implantation can achieve similar reduction of effective work function (WF) compared to alloying making it a candidate for CMOS integration. We complement our previous work on WF modulation by Yb on NiSi/SiON with new data on NiSi/HfSiON and NiGeSi/HfSiON. On the pFET, we study the effect of Al and Pt on Ni-rich FUSI and integrate it with a SiGe-channel. Integration into our reference devices resulted in a V_t reduction from 0.55/0.61V down to 0.30/0.25V for nFET (NiSi:Yb gate) and pFET (Ni₂Si:Pt gate + SiGe channel) respectively on SiON without degradation of the dielectric integrity and long channel mobility, and without an increase in gate leakage and D_it
  VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on;