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J. Solid-State Circuits. 01/2012; 47:301-309.
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Kenjiro Fukuda,
Tsuyoshi Sekitani,
Ute Zschieschang,
Hagen Klauk,
Kazunori Kuribara,
Tomoyuki Yokota,
Takushi Sugino,
Kinji Asaka,
Masaaki Ikeda,
Hirokazu Kuwabara,
Tatsuya Yamamoto,
Kazuo Takimiya,
Takanori Fukushima,
Takuzo Aida, Makoto Takamiya,
Takayasu Sakurai,
Takao Someya
Advanced Functional Materials 09/2011; 21(21):4019 - 4027. · 10.18 Impact Factor
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Tomoyuki Yokota,
Takashi Nakagawa,
Tsuyoshi Sekitani,
Yoshiaki Noguchi,
Kenjiro Fukuda,
Ute Zschieschang,
Hagen Klauk,
Ken Takeuchi, Makoto Takamiya,
Takayasu Sakurai,
Takao Someya
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ABSTRACT: We have demonstrated threshold-voltage control of p- and n-channel organic transistors with a floating-gate structure and self-assembled monolayer-based gate dielectrics and applied this technique to tune the switching voltage of organic complementary inverters. The threshold voltages of the p- and n-channel transistors are changed independently and systematically across a wide range from +2.4 to –1 V and from –0.3 to +1.5 V, respectively, when the program voltages of –6 V and +6 V are applied to the p- and n-channel transistors, respectively. Furthermore, we fabricated tunable organic complementary inverters, and ring oscillators whose oscillations are controlled by varying floating-gate charges.
Applied Physics Letters 05/2011; 98(19):193302-193302-3. · 3.84 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: In this paper we present User Customizable Logic Paper (UCLP) with a Sea-of Transmission-Gates (SOTG) of 2-V organic CMOS transistors. This can enable users to fabricate custom integrated circuits, by printing 200 m wide interconnects with at-home ink-jet printers for the prototyping of large-area electronics and educational purposes. The SOTG reduces the area of the circuits in UCLP by between 11% and 85% compared with a conventional gate array architecture.
IEEE Journal of Solid-State Circuits 01/2011; 46. · 3.23 Impact Factor
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IEICE Transactions. 01/2011; 94-C:985-991.
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IEICE Transactions. 01/2011; 94-C:598-604.
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Proceedings of the 16th Asia South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, January 25-27, 2011; 01/2011
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IEICE Transactions. 01/2011; 94-C:953-959.
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Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010; 01/2011
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IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011; 01/2011
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IEICE Transactions. 01/2011; 94-C:1072-1075.
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IEICE Transactions. 01/2011; 94-C:938-944.
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IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011; 01/2011
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IEICE Transactions. 01/2010; 93-C:332-339.
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IEICE Transactions. 01/2010; 93-C:317-323.
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J. Solid-State Circuits. 01/2010; 45:249-259.
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IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings; 01/2010
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IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings; 01/2010
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IEICE Transactions. 01/2010; 93-C:796-802.
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IEEE International Conference on 3D System Integration, 3DIC 2010, Munich, Germany, 16-18 November 2010; 01/2010