T. Yoshinaga

Publications (2)1.1 Total impact

• Article: Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors

  H. Matsutani, M. Koibuchi, H. Amano, T. Yoshinaga
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  ABSTRACT: Multi and many-core applications are sensitive to interprocessor communication latencies, suggesting the need for low-latency on-chip networks. We propose a low-latency router architecture that predicts the output channel to be used by the next packet transfer and speculatively completes the switch arbitration to reduce communication latency. The packets coming into the prediction routers are transferred without waiting for the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing communication latency is the hit rates of the prediction algorithms, which vary based on network environments, such as the network topology, routing algorithm, and traffic pattern. Although typical low-latency routers that skip one or more pipeline stages use a bypass data path that is based on a static or single bypassing policy (e.g., accelerating the packets moving in the same dimension), our prediction router architecture predictively forwards packets based on the prediction algorithm selected from among several candidates in response to the network environment. We analyze the prediction hit rates of five prediction algorithms on meshes, tori, fat trees, and Spidergons. Then, we present four case studies, each of which assumes different many-core architectures. We implemented the prediction routers for each case study by using a 45 nm CMOS process, and evaluated them in terms of the prediction hit rate, zero-load latency, hardware amount, and energy consumption. A typical prediction router with two or three predictors shows that although the area and energy are increased by 4.8-12.0 percent and 5.3 percent, respectively, up to 89.8 percent of the prediction hit rate is achieved in real applications, which provides favorable trade-offs between modest hardware/energy overheads and significant latency saving.
  IEEE Transactions on Computers 07/2011; · 1.10 Impact Factor
• Source

  Available from: uec.ac.jp

  Conference Proceeding: Impact of Predictive Switching in 2-D Torus Networks

  T. Yoshinaga, H. Murakami, M. Koibuchi
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  ABSTRACT: Predictive switching is a technique for reducing message latency in parallel computer networks. It tries to decide traversal paths of messages by utilizing a prediction mechanism so that processing time for message headers can be shortened. A key issue of predictive switching is the overhead of prediction failures. This paper presents simple and efficient treatments of prediction failures. Our proposal includes three schemes. The first scheme is arranging predictive and non-predictive routers in a network to safely detect and discard mis-predicted packets. The second is additional hardware to reduce occurrences of mis-predicted packets. The third scheme is to shorten the mis-predicted packets. We show the impact of predictive switching embodying the three schemes for k-ary 2-cubes (k = 8, 16, 32) with dimension- order routing. Our simulation results demonstrate that we can reduce average message latency by minimizing the prediction-failure overhead. Network saturation throughput is also improved when the predictor's accuracy is high.
  Innovative architecture for future generation high-performance processors and systems, 2007. iwia 2007. international workshop on; 02/2007