Chih-Ho Tu

National Kaohsiung Normal University, Kao-hsiung-shih, Kaohsiung, Taiwan

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Publications (20)11.33 Total impact

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    ABSTRACT: A PMOS switching-biased VCO is investigated and fabricated by using TSMC 0.35 μm CMOS technology with 2.8 V power supply voltage. A switching bias is employed for the PMOS tail transistor to improve the phase noise. Measured tuning range is ranged from 2.87 GHz to 3.2 GHz. At 1 MHz offset from the carrier, the measured phase noise is -118.2 dBc/Hz. The chip takes 0.32 mm2 area. For a 0.35mm process, under the consideration of output power, this design shows better performance over the figure of merit.
    Microwave Conference Proceedings (APMC), 2013 Asia-Pacific; 01/2013
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    ABSTRACT: This paper investigates the down-converted mixer verification using the measured X-parameter in future system-level simulation. The X-parameter measurement system utilizing Agilent's nonlinear vector network analyzer (NVNA) and the external RF signal generator can provide the desired stimulus to device under test (DUT) at the specified port in order to measure and respond to the non-linear DUT characteristic. The X-parameter of the down-converted mixer may include the measured nonlinear output power and phase at the specified frequencies. Also, the down-converted mixer utilizing nonlinear device characteristic to convert RF to intermediate frequency (IF) can be described by the X-parameter with good consistency.
    Microwave Conference Proceedings (APMC), 2013 Asia-Pacific; 01/2013
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    ABSTRACT: In this paper, a concurrent dual-band folded-cascode mixer with a dual-band LC-tank biasing circuit is presented. The operation frequency bands of the dual-band mixer are around 2.3 GHz and 5.2 GHz, respectively. A topology of LC series-parallel resonance, which is located on the current-sinking path of the biasing circuit is used to arrive at a dual-band characteristic. An on-chip balun is designed to transform a single-ended signal, such as a radio-frequency input signal and a local oscillation signal, into a couple of differential signals for the presented mixer. The simulated/measured conversion gains are about 15.6 dB/13.4 dB and 11.3 dB/8.6 dB at 2.3 GHz and 5.2 GHz, respectively. The measured IIP3 is −6.7 dBm and −1.1 dBm at 2.3 GHz and 5.2 GHz, respectively. The RF reflection coefficients at both bands are below −8 dB. The measured single sideband noise factors, NFSSB, are about 12.1 dB and 16 dB at 2.3 GHz and 5.2 GHz, respectively. The DC power consumption of the core circuit is 7.52 mW under 1.6 V supply voltage.
    Microelectronics Journal 12/2012; 43(12):1010–1015. · 0.91 Impact Factor
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    ABSTRACT: This paper proposes a bit error rate (BER) measurement system utilizing vector signal analyzer (VSA) instrument built-in analog digital converter (ADC) and ideal digital baseband receiver of VSA software for RF integrated circuits (RFICs) such as RF amplifier, RF mixer and RF receiver. Usually, BER performance is estimated in transceiver with built-in digital baseband circuits. In the past, RF designers could not estimate RFICs effect to BER test without digital baseband circuits and vice versa for digital baseband designers. It is helpful to understand RFICs without digital baseband circuits to BER test can reduce certain risk before integrating RFICs with digital baseband circuits. Therefore, an implementation of output signal to noise ratio (SNR) calibration in a specified bandwidth and measurement method combined VSA instrument, VSA software and Advanced Design System (ADS) is used for BER measurement.
    Conference Record - IEEE Instrumentation and Measurement Technology Conference 01/2012;
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    ABSTRACT: A cascode class-E power amplifier (PA) operating at 5.2 GHz has been designed using Advanced Design System simulation. RF circuit performances such as output power and power-added efficiency before and after RF stress have been experimentally investigated. The measured output power, power-added efficiency, and linearity after high-input-power RF stress at elevated supply voltage show significant circuit degradations. The impact of hot-carrier injection and gate oxide soft breakdown on cascode class-E PA reliability is discussed.
    IEEE Transactions on Device and Materials Reliability 01/2012; 12(2):369-375. · 1.52 Impact Factor
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    ABSTRACT: The radiation of a line source is extended to analyze the radiation fields of bond wire antennas with basic antenna theory. The comparison of numerical and simulation results shows in good agreement. The presented estimation method provides a quick way for antenna engineers to design bond wire antennas with appropriate main beam directions, which are useful in inter-chip wireless communications.
    Antennas and Propagation Society International Symposium (APSURSI), 2012 IEEE; 01/2012
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    ABSTRACT: The performances and reliability of the NMOS power cells for power amplifiers (PA) were proposed. The performances of power cells with different layout geometries have been compared. The drain current degradation of the NMOS transistors due to hot-carrier effect and high RF power stresses induced by the load impedance mismatches was also present in this work. The load mismatch factors at fundamental, second-order, and third-order frequencies were analyzed to quantify the power mismatch. The cells were fabricated by a 0.18 μm CMOS process. All of the characteristics of the devices were measured at 5.2 GHz.
    IEEE Microwave and Wireless Components Letters 01/2011; · 1.78 Impact Factor
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    ABSTRACT: Both the degradations of dc and RF characteristics of nMOS transistors due to hot-carrier effect and instantaneous high RF power stresses are presented in this paper. The drain current, threshold voltage, output power, and power-added efficient were degraded after the output power exceeded the power capacity. At this condition, the voltage between drain and gate became large and made the oxide soft breakdown happen. The load-pull system is used to set up the measurement for optimized input and output power matching networks. The shift of the optimum load impedance and constant power-gain circles for power match indicated that the parameters of the stressed cells were changed by the damage in the gate oxide. The signal distortion, gate voltage swing, and thermal effect were all considered in this paper. The cells were fabricated by a 0.18-μm CMOS process. All of the characteristics of the devices were measured at 5.2 GHz.
    IEEE Transactions on Device and Materials Reliability 10/2010; · 1.52 Impact Factor
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    ABSTRACT: In this paper, a design for high dynamic range applicable of power detector by using successive detection logarithmic amplifier (SDLA) configuration consists of PMOS load limiting amplifier and unbalanced source-coupled pairs. This device was been fabricated by TSMC 0.18-¿m 1P6M CMOS process. The experimental results show that the dynamic range of the power detector the frequency 900-MHz is almost kept at 39-dB and for frequency 1800-MHz, the dynamic range is 29-dB. Its log-error is kept at ±1-dB and consumes is 16-mW from a 1.8-V supply.
    01/2009;
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    ABSTRACT: A RF tunable active bandpass filter with active inductor using Q-enhancement circuit is presented. The RF active filter was implemented by the TSMC 0.35 mum 3P3M BiCMOS process. In order to improve the quality factor of the active inductor, the Q-enhancement circuit was used to compensate the loss of the active inductor. The insertion loss of the RF tunable active filter is about 0.5dB, and the tuning range of center frequency is from725MHz to 2050MHz.
    Innovative Computing ,Information and Control, International Conference on. 01/2009;
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    ABSTRACT: In this letter, we investigate the performance degradation of nMOS transistors due to hot-carrier effect and load impedance mismatch. The DC and radio-frequency characteristics, such as drain current, threshold voltage, transconductance, output power, power-added efficiency, etc., are affected under hot-carrier effect. With load impedance mismatch, the transistors experience the reflected power from load and increase the energy of hot carriers. This effect will make DC and power performances degenerate heavily. In this letter, device characteristics were measured at 5.2 GHz.
    IEEE Electron Device Letters 10/2008; · 2.79 Impact Factor
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    ABSTRACT: In this work, a novel architecture with stacked-type CMOS device is presented. The reformed CMOS switch was implemented by the TSMC 0.18 um 1P6M standard CMOS process. In order to improve power handling capability and strengthen the isolation, the proposed circuit is inserted with an excess transistor adjacent to the receiver side. The insertion loss of the designed CMOS T/R switch is about 1.9plusmn0.3 dB. The isolation is greater than 25 dB and the power handling is capable of 28 dBm at 5.8 GHz.
    01/2008;
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    ABSTRACT: In this paper, we investigate the performance degradation of nMOS transistors due to hot-carrier effect and drain power mismatch. The DC and RF characteristics, such as drain current, threshold voltage, transconductance, power gain, etc., are affected under some kinds of stresses. During the power contour measurement by a load-pull system, the transistors experience the reflection power from load for the most part of measurement time. This mainly results from mismatching impedance and will make drain current degenerated. The degree of the degeneration depends on the quantity of load mismatch and device layout pattern of power cells. From the measurement results, it is found that the degradation can be mitigated by a dispersive layout structure. From the experimental results, the layout of power cells can be designed properly to mitigate the degeneration of power performances and improve the reliability of circuits when designing CMOS RF power amplifiers. The power performances of this paper were measured at 5.2 GHz.
    Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on; 09/2007
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    ABSTRACT: A dual band-notched monopole antenna with an annular coplanar waveguides feeding structure for ultra-wideband (UWB) application is proposed, in which the ring in the feeding structure is used to increase the impedance bandwidth, and two quarter-wavelength tuning stubs inserted into the proposed feeding ring and radiating ring, respectively, creates two band-notches at 5.15 and 5.75 GHz across the UWB frequency band from 2.6 to 12 GHz. The novel design is quiet compact and suitable for creating UWB antenna with dual narrow frequency notches. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 2376–2379, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22748
    Microwave and Optical Technology Letters 07/2007; 49(10):2376 - 2379. · 0.59 Impact Factor
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    ABSTRACT: An implantable rectenna with stacked PIFA structure has been developed for wireless power transmission for medical implants in 402-405 MHz (MICS Band). The antenna has dimension of 450 mm<sup>3</sup> measured operating frequency of 402 MHz with broad bandwidth of 50 MHz at return loss -10 dB. Experimental prototype of the compact stacked rectenna was fabricated on Roger 3210 substrate. The rectenna has a conversion efficiency of 80% is achieved when 2dBm microwave power is received at 402 MHz with 20K- Omega load.
    Antennas and Propagation Society International Symposium, 2007 IEEE; 07/2007
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    ABSTRACT: A broadband disk monopole antenna with a circular CPW-feeding line is proposed, which is composed of a circular CPW fed with a 50 Omega CPW line through a disk radiator. A parametric study was carried out to optimize the proposed structure, and the measured results show that the proposed design can obtain a very wide impedance bandwidth of 126% (from 2.7~12 GHz) with omni-directional radiation patterns over the entire bandwidth. Furthermore, the measure antenna peak gain range is 2.3~5.0 dBi for frequencies across the UWB operation.
    Antennas and Propagation Society International Symposium, 2007 IEEE; 07/2007
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    ABSTRACT: A dual-band notched printed disk monopole antenna with circular coplanar waveguides (CPW) feeder for ultra-wideband (UWB) application is proposed, in which the circular CPW feeder is used to increase the impedance bandwidth, and by inserting two quarter-wavelength U-slots on the proposed circular CPW feeder and disk radiating element, respectively, two band-notches at 5.15 GHz and 5.75 GHz are obtained across the UWB frequency band from 2.6-12 GHz. Thus, the novel design is suitable for creating UWB printed antenna with dual narrow frequency notches.
    Wireless and Microwave Technology Conference, 2006. WAMICON '06. IEEE Annual; 01/2007
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    ABSTRACT: This paper presents a full integrated 2.4GHz inductively degenerated cascode low noise amplifier (LNA) realized in a standard TSMC 0.25-μm CMOS process. The source degenerated inductor has been design after the electromagnetic (EM) analysis using the calibrated substrate conditions. The measured performance of the proposed LNA shows the noise figure (NF) of 2.87 dB, the power gain of 13.29 dB, and the reverse isolation of -30.8 dB. High linearity design with the output 1 dB gain compression point (PldB) of 0 dBm, input third-order intercept point (IIP3) of 2.2 dBm, and the power consumption is only 11 mW while dissipating 5.5 mA from a 2 V supply. The overall measured results of the implemented LNA show good agreement with simulated results.
    VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
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    ABSTRACT: This work presents a fully integrated 5.2 GHz inductively degenerated low noise amplifier (LNA) design fully integrated in a TSMC 0.25 μm CMOS process. We design a 0.516nH minute inductor as a source inductor by the EM analysis of the ADS. The designed LNA consumes 11.9 mW DC power. At 5.2 GHz, this fabricated LNA has noise figure (NF) of 3.54 dB, with input return loss of -15.29 dB, output return loss of -18.1 dB, and voltage gain of 11.78 dB. The simulated and measured results are approximate.
    Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on; 01/2005
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    ABSTRACT: The impacts of various layout configuration and device dimensions on device performance are examined. The geometrical scaling issues including emitter length and emitter stripe-number scaling are used to shift simultaneously the optimum noise and optimum source impedance to a point that is close to 50 Ω. Via this method, not only is the optimal transistor size for low-noise applications obtained, but the matching network is simplified to reduce the losses of passive networks and the chip area. Based on experimental results, optimum SiGe HBTs and bias suitable for low-noise amplifiers (LNAs) are determined. Via the comparison of the state-of-the-art SiGe LNAs, it is confirmed that this method is effective to obtain better performances. Using the same method, the optimum device size at any bias and any frequency for low-noise applications can also be achieved.
    IEEE Transactions on Microwave Theory and Techniques 10/2004; · 2.23 Impact Factor