Swaroop Ghosh

Publications (17)1.27 Total impact

• Article: Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking.

  Swaroop Ghosh, Kaushik Roy
  IEEE Trans. VLSI Syst. 01/2011; 19:1504-1507.
• Source

  Available from: lirmm.fr

  Conference Proceeding: Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost.

  Ashish Goel, Swaroop Ghosh, Mesut Meterelliyoz, Jeff Parkhurst, Kaushik Roy
  Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011; 01/2011
• Article: Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking.

  Swaroop Ghosh, Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy
  IEEE Trans. VLSI Syst. 01/2010; 18:1301-1309.
• Article: Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths.

  Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
  IEEE Trans. VLSI Syst. 01/2010; 18:53-65.
• Source

  Available from: purdue.edu

  Conference Proceeding: A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking

  Swaroop Ghosh, Patrick Ndai, Kaushik Roy
  [show abstract] [hide abstract]
  ABSTRACT: As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to avoid shorts/opens/bridges. However, it is not possible to completely eliminate the possibility of such defects. If spare units are not present to replace the defective parts, then such failures cause yield loss. In this paper, we present a fault tolerant technique to leverage the redundancy present in high speed regular circuits such as Kogge-Stone adder (KSA). Due to its regularity and speed, KSA is widely used in ALU design. In KSA, the carries are computed fast by computing them in parallel. Our technique is based on the fact that even and odd carries are mutually exclusive. Therefore, defect in even bit can only corrupt the even Sum outputs whereas the odd Sums are computed correctly (and vice versa). To efficiently utilize the above property of KSA in presence of defects, we perform addition in two- clock cycles. In cycle-1, one of the correct set of bits (even or odd) are computed and stored at output registers. In cycle-2, the operands are shifted by one bit and the remaining sets of bits (odd or even) are computed and stored. This allows us to tolerate the defect at the cost of throughput degradation while maintaining high frequency and yield. The proposed technique can tolerate any number of faults as long as they are confined to either even or odd bits (but not in both).
  Design, Automation and Test in Europe, 2008. DATE '08; 04/2008
• Article: An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.

  Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy
  JETC. 01/2008; 4.
• Conference Proceeding: O

  Swaroop Ghosh, Jung Hwan Choi, Patrick Ndai, Kaushik Roy
  Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008; 01/2008
• Source

  Available from: psu.edu

  Article: Low-Power and testable circuit synthesis using Shannon decomposition.

  Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
  ACM Trans. Design Autom. Electr. Syst. 01/2007; 12.
• Source

  Available from: cecs.uci.edu

  Article: CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation.

  Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
  IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2007; 26:1947-1956.
• Source

  Available from: psu.edu

  Conference Proceeding: Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.

  Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
  2007 Design, Automation and Test in Europe Conference and Exposition (DATE 2007), April 16-20, 2007, Nice, France; 01/2007
• Conference Proceeding: Tolerance to Small Delay Defects by Adaptive Clock Stretching.

  Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy
  13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece; 01/2007
• Source

  Available from: case.edu

  Article: A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor

  Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
  [show abstract] [hide abstract]
  ABSTRACT: A novel integrated approach for delay-fault testing in external (automatic-test-equipment-based) and test-per-scan built-in self-test (BIST) using on-die delay sensing and test point insertion is proposed. A robust, low-overhead, and process-tolerant on-chip delay-sensing circuit is designed for this purpose. An algorithm is also developed to judiciously insert delay-sensor circuits at the internal nodes of logic blocks for improving delay-fault coverage with little or no impact on the critical-path delay. The proposed delay-fault testing approach is verified for transition- and segment-delay-fault models. Experimental results for external testing (BIST) show up to 31% (30%) improvement in fault coverage and up to 67.5% (85.5%) reduction in test length for transition faults. An increase in the number of robustly detectable critical-path segments of up to 54% and a reduction in test length for the segment-delay-fault model of up to 76% were also observed. The delay and area overhead due to insertion of the delay-sensing hardware have been limited to 2% and 4%, respectively
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 01/2007; · 1.27 Impact Factor
• Source

  Available from: psu.edu

  Conference Proceeding: Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.

  Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy
  Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006; 01/2006
• Conference Proceeding: Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.

  Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
  12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy; 01/2006
• Conference Proceeding: A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation.

  Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
  2006 International Conference on Computer-Aided Design (ICCAD'06), November 5-9, 2006, San Jose, CA, USA; 01/2006
• Conference Proceeding: A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning.

  Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
  11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France; 01/2005
• Article: O 2 C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors

  Swaroop Ghosh, Jung-Hwan Choi, Patrick Ndai, Kaushik Roy
  [show abstract] [hide abstract]
  ABSTRACT: In this paper, we propose O2C, a novel non-speculative adaptive thermal management technique that reduces the temperature during die-overheating using supply voltage scaling, while maintaining the rated clock frequency. This is accomplished by (a) scaling down the supply voltage, (b) isolating and predicting the set of critical paths, (c) ensuring (by design) that they are activated rarely, and (d) getting around occasional delay failures (at reduced voltage during die-overheating) in these paths by two-cycle operations (assuming all standard operations are single-cycle). Two-cycle operation is achieved by stalling the pipeline for extra clock cycles whenever the set of critical paths are activated. The rare two-cycle operation results in a small decrease in IPC (instructions per cycle). Since called O2C maintains the rated clock frequency and does not require pipeline stalling during supply voltage ramp-up/ramp-down, it achieves high throughput in a thermally constrained environment. We applied called O2C to the integer execution units of an in-order superscalar pipeline. Standard full-chip Dynamic Voltage-Frequency Scaling (DVFS) is very effective in bringing down the temperature, however; it is associated with large throughput loss due to pipeline stalling and slow operating frequency during thermal management. We integrated "O2C with standard DVFS" (called O2Cα) to demonstrate that it can act as a "first step" before full-scale thermal management is required. Our simulations indeed reveal that called O2Cα policy can avoid the requirement of full-scale DVFS during execution of programs.