Walter M. Weber

NaMLab GmbH, Dresden, Saxony, Germany

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Publications (47)111.55 Total impact

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    ABSTRACT: The physical and electrical properties of a silicon nanowire reconfigurable field effect transistor (RFETs) are determined by the Schottky junction between the participating phases. TEM studies on such junctions require a careful FIB-based target preparation of thin lamellae with minimal ion-beam induced damage. In the current study, the nickel silicide phase forming the Schottky junction with silicon is identified using EDX in the TEM, considering a calibration based on the Fourier transforms of the HRTEM micrographs of known diffraction patterns of the nickel silicide phases. The TEM lamellae are prepared using the so-called lift-out technique and low voltage Ga+ ion polishing to minimize the near-surface amorphization. The structural and compositional data of the nickel silicide phase are needed for engineering the Schottky junction and corresponding theoretical modeling.
    Advanced Engineering Materials 03/2015; DOI:10.1002/adem.201400577 · 1.51 Impact Factor
  • Symposium LL – Semiconductor Nanowires—Growth, Physics, Devices and Applications; 01/2015
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    ABSTRACT: A novel photosensitive hybrid field‐effect transistor (FET) which consists of a multiple‐shell of organic porphyrin film/oxide/silicon nanowires is presented. Due to the oxide shell around the nanowires, photoswitching of the current in the hybrid nanodevices is guided by the electric field effect, induced by charge redistribution within the organic film. This principle is an alternative to a photoinduced electron injection, valid for devices relying on direct junctions between organic molecules and metals or semiconductors. The switching dynamics of the hybrid nanodevices upon violet light illumination is investigated and a strong dependence on the thickness of the porphyrin film wrapping the nanowires is found. Furthermore, the thickness of the organic films is found to be a crucial parameter also for the switching efficiency of the nanowire FET, represented by the ratio of currents under light illumination (ON) and in dark conditions (OFF). We suggest a simple model of porphyrin film charging to explain the optoelectronic behavior of nanowire FETs mediated by organic film/oxide/semiconductor junctions.
    Nano Research 11/2014; DOI:10.1007/s12274-014-0608-7 · 7.39 Impact Factor
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    ABSTRACT: Reconfigurable nanowire transistors are multifunctional switches that fuse the electrical characteristics of unipolar n- and p-type field effect transistors (FETs) into a single universal type of four-terminal device. In addition to the three known FET electrodes the fourth acts as an electric select signal that dynamically programs the desired polarity. The transistor consists of two independent charge carrier injection valves as realized by two gated Schottky junctions integrated within an intrinsic silicon nanowire. The transport properties that provide unipolar n- and p-type behavior will be elucidated. Further, solutions to the major device challenges toward the implementation of these novel transistors at the circuit level are proposed, by exploiting specific nanowire geometries and dimensions. These include methods that deliver equal on-currents and symmetric transfer characteristics for n- and p-type, and that eliminate supra-linear output characteristics at low source-drain biases. We will further show that circuits built of these symmetric transistors successfully exhibit complementary operation. Finally, the prospects in building reconfigurable circuits and systems will be briefly summarized.
    IEEE Transactions on Nanotechnology 11/2014; 13(6):1020. DOI:10.1109/TNANO.2014.2362112 · 1.62 Impact Factor
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    ABSTRACT: In this work, we investigate the temperature dependence of electrical switching properties of back-gated, undoped Si-nanowire field-effect transistors with Ni-silicided source/drain contacts. A simple, phenomenological model illustrates the leading order temperature dependence of the source-drain current, which originates predominantly from charge carrier injection by tunneling through the Schottky junction. Drain current versus gate voltage measurements have been performed for various temperatures and several drain voltages on a single nanowire device. The temperature dependence of the drain-source current for specific gate and drain voltages is analysed within the framework of voltage dependent effective barrier heights. As a result, the temperature dependence of the tunnelling current is not only important for the sub-threshold region, but also plays a significant role in the transistor “on-state”. In addition, the effective barrier heights for electrons and holes tend towards the natural Schottky barriers of the NiSi2-Si interface, if the applied external fields generate the case of flat band condition at the injection Schottky barrier, i.e. in the deep “off-state” region. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)
    physica status solidi (c) 11/2014; 11(11-12). DOI:10.1002/pssc.201400055
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    ABSTRACT: Growth experiments show significant differences in crystallization of ultrathin CaTiO3 layers on polycrystalline Pt surfaces. While the deposition of ultrathin layers below crystallization temperature inhibits the full layer crystallization, local epitaxial growth of CaTiO3 crystals on top of specific oriented Pt crystals occurs. The result is a formation of crystals embedded in an amorphous matrix. An epitaxial alignment of the cubic CaTiO3 <111> direction on top of the underlying Pt {111} surface has been observed. A reduced forming energy is attributed to an interplay of surface energies at the {111} interface of both materials and CaTiO3 nanocrystallites facets. The preferential texturing of CaTiO3 layers on top of Pt has been used in the preparation of ultrathin metal-insulator-metal capacitors with 5-30 nm oxide thickness. The effective CaTiO3 permittivity in the capacitor stack increases to 55 compared to capacitors with amorphous layers and a permittivity of 28. The isolated CaTiO3 crystals exhibit a passivation of the CaTiO3 grain surfaces by the surrounding amorphous matrix, which keeps the capacitor leakage current at ideally low values comparable for those of amorphous thin film capacitors.
    ACS Applied Materials & Interfaces 10/2014; DOI:10.1021/am504831q · 5.90 Impact Factor
  • Microscopy and Microanalysis 08/2014; 20(S3):360-361. DOI:10.1017/S1431927614003523 · 1.76 Impact Factor
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    ABSTRACT: A feasibility and performance study of electrically reconfigurable nanowire transistors with selectable pFET and nFET operations is presented. The challenges toward circuit implementation are evaluated based on transient simulations of logic circuits. A novel physical structure capable of computing a NAND as well as NOR function is introduced. The new approach provides a flexible platform to develop and test fine-grain reconfigurable circuits and systems.
    IEEE Electron Device Letters 01/2014; 35(1):141-143. DOI:10.1109/LED.2013.2290555 · 3.02 Impact Factor
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    ABSTRACT: Reconfigurable fine-grain electronics target an increase in the number of integrated logic functions per chip by enhancing the functionality at the device level and by implementing a compact and technologically simple hardware platform. Here we study a promising realization approach by employing reconfigurable nanowire transistors (RFETs) as the multifunctional building-blocks to be integrated therein. RFETs merge the electrical characteristics of unipolar n- and p- type FETs into a single universal device. The switch comprises four terminals, where three of them act as the conventional FET electrodes and the fourth acts as an electric select signal to dynamically program the desired switch type. The transistor consists of two independent charge carrier injection valves as represented by two gated Schottky junctions integrated within an intrinsic silicon nanowire. Radial compressive strain applied to the channel is used as a scalable method to adjust n- and p-FET currents to each other, thereby enabling complementary logic circuits. Simple but relevant examples for the reconfiguration of complete gates will be given, demonstrating the potential of this technology.
    Design Automation and Test in Europe; 01/2014
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    ABSTRACT: Reconfigurable nanowire transistors provide the operation of unipolar p-type and n-type FETs freely selectable within a single device. The enhanced functionality is enabled by controlling the currents through two individually gated Schottky junctions. Here we analyze the impact of the Schottky barrier height on the symmetry of Silicon nanowire RFET transfer characteristics and their performance within circuits. Prospective simulations are carried out, indicating that germanium nanowire based RFETs of the same dimensions will show a distinctly increased performance, making them a promising material solution for future reconfigurable electronics.
    MRS Online Proceeding Library 01/2014; 1659. DOI:10.1557/opl.2014.110
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    Optoelectronic and Microelectronic Materials & Devices (COMMAD), 2014 Conference on; 01/2014
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    ABSTRACT: Silicon nanowires offer unique properties like inherent small diameters, quasi 1-dimensional current transport and the flexibility to combine materials that cannot be combined in bulk or thin film structures. Based on these properties electron devices, sensors as well as solar cells and lithium batteries can be envisioned that significantly outperform their thin film or bulk counterparts. The expectation, that the ultimate MIS device will be based on silicon nanowires gives this technology the potential for a seamless integration into integrated electronic systems. This paper gives an overview of important device applications of silicon nanowires. Starting with nanowire fabrication, the different device concepts and their important features will be introduced.
    physica status solidi (RRL) - Rapid Research Letters 10/2013; 7(10):793-799. DOI:10.1002/pssr.201307247 · 2.34 Impact Factor
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    ABSTRACT: Reconfigurable Nanowire Transistors merge the electrical properties of unipolar n- and p- type FETs into a single type of device with identic technology, geometry and composition. These four-terminal nanowire transistors employ an electric signal to dynamically program unipolar n- or p-type behavior. More than reducing the technological complexity, they open up the possibility of dynamically programming the functions of circuits at the device level, i.e. enabling a fine-grain reconfiguration of complex functions. We will review different reconfigurable concepts, analyze the transport properties and finally assess their maturity for building circuits.
    Solid-State Device Research Conference (ESSDERC), 2013 Proceedings of the European; 09/2013
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    ABSTRACT: We present novel multifunctional nano-circuits built from nanowire transistors that uniquely feature equal electron and hole conduction. Thereby, the mandatory requirement to yield energy efficient circuits with a single type of transistor is shown for the first time. Contrary to any transistor reported up to date, regardless of the technology and semiconductor materials employed, the dually active silicon nanowire channels shown here exhibit an ideal symmetry of current-voltage device characteristics for electron (n-type) and hole (p-type) conduction as evaluated in terms of comparable currents, turn-on threshold voltages and switching slopes. The key enabler to symmetry is the selective tunability of the tunneling transmission of charge carriers as rendered by the combination of the nanometer-scale dimensions of the junctions and the application of radially compressive strain. To proof the advantage of this concept we integrated dually active transistors into cascadable and multi-functional one-dimensional circuit strings. The nano-circuits confirm energy efficient switching and can further be electrically configured to provide four different types of operation modes compared to a single one when employing conventional electronics with the same amount of transistors.
    Nano Letters 08/2013; 13(9). DOI:10.1021/nl401826u · 13.03 Impact Factor
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    ABSTRACT: Over the past years, high-k dielectrics have been incorporated into modern semiconductor devices. One example is ZrO2, which has been introduced in memory applications. This paper elucidates some difficulties with pure ZrO2 like unintended crystallization during the growth of the dielectric and the evolution of the monoclinic phase, which reduces the k-value. The admixture of Sr is shown as a solution to circumvent those issues. A detailed structural analysis for a varying stoichiometry ranging from pure ZrO2 to the perovskite SrZrO3 is given. The detected crystal structures are correlated to our observations of the dielectric properties obtained by an electrical characterization. (C) 2013 AIP Publishing LLC.
    Journal of Applied Physics 06/2013; 113(22-22). DOI:10.1063/1.4811226 · 2.19 Impact Factor
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    ABSTRACT: We present novel Schottky barrier field effect transistors consisting of a parallel array of bottom-up grown silicon nanowires that are able to deliver high current outputs. Axial silicidation of the nanowires is used to create defined Schottky junctions leading to on/off current ratios of up to 10(6). The device concept leverages the unique transport properties of nanoscale junctions to boost device performance for macroscopic applications. Using parallel arrays, on-currents of over 500 mu A at a source-drain voltage of 0.5 V can be achieved. The transconductance is thus increased significantly while maintaining the transfer characteristics of single nanowire devices. By incorporating several hundred nanowires into the parallel array, the yield of functioning transistors is dramatically increased and deviceto-device variability is reduced compared to single devices. This new nanowirebased platform provides sufficient current output to be employed as a transducer for biosensors or a driving stage for organic light-emitting diodes (LEDs), while the bottom-up nature of the fabrication procedure means it can provide building blocks for novel printable electronic devices.
    Nano Research 06/2013; 6(6-6):381-388. DOI:10.1007/s12274-013-0315-9 · 6.96 Impact Factor
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    ABSTRACT: Metal-Insulator-Metal capacitors, with ZrO2/Al2O3/ZrO2 (ZAZ)-nanolaminate thin-films as a dielectric layer, exhibit reduced leakage currents compared to corresponding capacitors based on pure ZrO2 while maintaining a sufficiently high dielectric constant for the DRAM application. This work is a comparative study demonstrating how the incorporation of a small amount of Al is responsible for the suppression of crystallization during deposition. Extensive electrical characterization leads to the identification of a defect band which conductive atomic force microscopy shows to be formed along crystallite grain boundaries, extending through the entire ZrO2-film. The incorporation of a sub-layer of Al2O3 prevents these grain boundaries resulting in an effective reduction of leakage currents, despite the film being in the nanocrystalline phase, necessary for it to exhibit the required high dielectric constant. A transport model based on phonon assisted trap to trap tunneling is proposed. (C) 2013 AIP Publishing LLC.
    Journal of Applied Physics 05/2013; 113(19-19). DOI:10.1063/1.4804670 · 2.19 Impact Factor
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    ABSTRACT: Surface functionalization of NiSi2-Si-NiSi2 nanowire heterostructures, acting as Schottky-junction field effect transistors (SB-FETs) represent a promising route for biosensor applications. Axially Ni- silicidized silicon nanowires exhibit a very sharp metal-semiconductor interface, thus forming a well defined and reproducible Schottky barrier. These barriers determine the current through the wire and can be changed by small molecules chemiadsorbed on the nanowire surface. We report that surface modifications can alter the polarity of the devices. This severe influence on the charge transport implies ultrahigh sensitivity for nanowire SB-FETs.
    Proceedings of IMCS 2012 – The 14th International Meeting on Chemical Sensors, Nuremburg; 05/2012

Publication Stats

340 Citations
111.55 Total Impact Points

Institutions

  • 2014
    • NaMLab GmbH
      Dresden, Saxony, Germany
  • 2013
    • Technische Universität Dresden
      Dresden, Saxony, Germany
  • 2006–2008
    • University of Technology Munich
      • Institute of Nanoelectronics
      München, Bavaria, Germany